Hi Wade,
Yes, I have the ctrlport:has_status set to False in the block YAML... I
ended up having to comment out that test sequence to move onto the part
that sends samples into and out of the block; now I have an error that
states
*Fatal: Timeout: Test "Test passing through samples" time limit exceeded*
so I must be doing something that it isn't liking :) I've attached my
updated .v and .sv files that I modified based on your guidance in your
first response, as well as the updated xsim.log. Please let me know if
there are any additional things I may need to change such as sizes and what
not - thanks!
-Jeff
On Mon, May 9, 2022 at 3:12 PM Wade Fife <wade.f...@ettus.com> wrote:
> Hi Jeffrey,
>
> Very curious that you're getting that CTRL_STS_OKAY error, since it looks
> like you're not using the status. I assume ctrlport:has_status is set to
> False in your block's YAML? In that case the status should always be OK.
>
> 1) For different input/output packet sizes, you need to modify the context
> to set the payload length of the outgoing packet. That's the block of code
> starting on line 283 in the rfnoc_block_conv.v file you sent. There's an
> example in rfnoc_block_logpower, in which the output packet length is half
> the length of input packets. In your case you'll need to set it to 3/2
> instead of 1/2. See here:
>
>
> https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr.v#L202
> <https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_EttusResearch_uhd_blob_master_fpga_usrp3_lib_rfnoc_blocks_rfnoc-5Fblock-5Flogpwr_rfnoc-5Fblock-5Flogpwr.v-23L202&d=DwMFaQ&c=-35OiAkTchMrZOngvJPOeA&r=Y3cOHwFMBDXttsqnINKoCyXB-ta6yD08QrmMzW9aeZY&m=GXbgyQxDz4yiy7ZI94I9ia-1XvF2rdmrbxprVfQojmcljlWVOVrjE1Z7g7qsBL_a&s=WkFBbmpL8IpvF2oHp-4Vfhy73qA49jSJD2tHoTQ0anQ&e=>
>
> 2) The testbenches typically have an ITEM_W constant that indicates the
> size of the data type you want to work with. The ITEM_W is normally set to
> the sample size (e.g., 32 for sc16 samples). Since you want to work with
> bytes, you could change that to 8 then create an item_t array and send it
> as a single packet using blk_ctrl.send_items(). Then you can call
> blk_ctrl.recv_items() to get the data output packet, and inspect the items
> array that is returned. Take a look at PkgRfnocBlockCtrlBfm to see what
> other send/recv methods are available. Here's a quick example assuming the
> item size is 8-bit:
>
> item_t sent[$], received[$];
> sent = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }; // Whatever values you want for
> the input packet, one byte per element
> blk_ctrl.send_items(0, sent);
>
> blk_ctrl.recv_items(0, received);
> foreach(received[i]) begin
> // Compare the expected value to the byte in received[i] and see if it
> matches
> end
>
> Wade
>
> On Mon, May 9, 2022 at 1:30 PM Jeffrey Cuenco via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hi all,
>>
>> Long time no see! I am currently on a final stretches of completing a
>> masters project for my wireless embedded systems program that involves a
>> USRP X310 with RFNoC 4.0 and GNURadio that implements a Hierarchical
>> Modulation design using nested 4QAM / QPSK (final constellation "appears"
>> like 16QAM but has embedded high priority and low priority layers that can
>> adapt based on SNR).
>>
>> I am currently attempting to integrate the Xilinx Convolutional Encoder
>> v9.0 IP block into the template rfnoc_block_conv.v design that was created
>> using rfnocmodtool and modeled after the Ettus FFT example. With a bit of
>> work I was able to get the .xci file loaded by Vivado when the make target
>> is executed for the testbench, and the testbench appears to build without
>> much modification.
>>
>> When executing 'make rfnoc_block_conv_tb' it appears to fully execute
>> the build process to the end, but I receive a fatal "Did not receive
>> CTRL_STS_OKAY status" message in the process which I attribute to either
>> something not being configured in the testbench file or something not being
>> configured right in my verilog module file.
>>
>> I've attempted to summarize where I'm stuck and need help on in the below
>> three summary points / questions:
>> 1) I have configured the convolutional encoder with rate 1/2 and
>> punctured (effective rate 2/3), which I assume will require me modifying
>> the "axi_wrapper" so that the output to input ratios are set properly - are
>> there additional examples that I can follow for this?
>>
>> I've seen the axi_wrapper migration note but as I'm still a novice at
>> Verilog and System Verilog additional examples would be helpful. :)
>>
>>
>> 2) I would like to modify my testbench so that I send 10 bytes (80 bits)
>> of data, and read out the 15 bytes (120 bits) that get spit out and verify
>> that the encoded bytes coming out of the core match ground truth data I
>> would generate using MATLAB.
>>
>> Do we have any additional testbench examples or additional documentation
>> that show sending 1 or more bytes of data through an IP core? The IP core's
>> *s_axis_data_tdata* and *m_axis_data_tdata *are 8-bit while most of the
>> examples show sending 32 bits. Aside from setting the assignments to [7:0]
>> are there any other adjustments that need to be made in any of the signal
>> declarations and/or block definition wires earlier in the file?
>>
>> I've provided the IP core documentation for reference just in case:
>> https://docs.xilinx.com/v/u/en-US/pg026_convolution
>> <https://urldefense.proofpoint.com/v2/url?u=https-3A__docs.xilinx.com_v_u_en-2DUS_pg026-5Fconvolution&d=DwMFaQ&c=-35OiAkTchMrZOngvJPOeA&r=Y3cOHwFMBDXttsqnINKoCyXB-ta6yD08QrmMzW9aeZY&m=GXbgyQxDz4yiy7ZI94I9ia-1XvF2rdmrbxprVfQojmcljlWVOVrjE1Z7g7qsBL_a&s=VpTL0Eev0xGrPxywg6lGumMok1Lx8kj5t4uFefeMWNA&e=>
>>
>> I've also included the module and testbench files as well as the xsim log.
>>
>> Thanks in advance!
>> -Jeff
>>
>> _______________________________________________
>> USRP-users mailing list -- usrp-users@lists.ettus.com
>> To unsubscribe send an email to usrp-users-le...@lists.ettus.com
>>
>
#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Wed May 11 02:15:36 2022
# Process ID: 425419
# Current directory: /home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv
# Command line: vivado -mode batch -source /home/wes/capstone/usrp/uhd/fpga/usrp3/tools/scripts/viv_sim_project.tcl -log xsim.log -nojournal
# Log file: /home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/xsim.log
# Journal file:
#-----------------------------------------------------------
source /home/wes/capstone/usrp/uhd/fpga/usrp3/tools/scripts/viv_sim_project.tcl
# set simulator $::env(VIV_SIMULATOR)
# set design_srcs $::env(VIV_DESIGN_SRCS)
# set sim_srcs $::env(VIV_SIM_SRCS)
# set inc_srcs $::env(VIV_INC_SRCS)
# set sim_top $::env(VIV_SIM_TOP)
# set part_name $::env(VIV_PART_NAME)
# set sim_runtime $::env(VIV_SIM_RUNTIME)
# set sim_fast $::env(VIV_SIM_FAST)
# set vivado_mode $::env(VIV_MODE)
# set verilog_defs $::env(VIV_VERILOG_DEFS)
# set working_dir [pwd]
# set sim_fileset "sim_1"
# set project_name "[string tolower $simulator]_proj"
# if [info exists ::env(VIV_SIM_COMPLIBDIR) ] {
# set sim_complibdir $::env(VIV_SIM_COMPLIBDIR)
# if [expr [file isdirectory $sim_complibdir] == 0] {
# set sim_complibdir ""
# }
# } else {
# set sim_complibdir ""
# }
# if [expr ([string equal $simulator "XSim"] == 0) && ([string length $sim_complibdir] == 0)] {
# puts "BUILDER: \[ERROR\]: Could not resolve the location for the compiled simulation libraries."
# puts " Please build libraries for chosen simulator and set the env or"
# puts " makefile variable SIM_COMPLIBDIR to point to the location."
# exit 1
# }
# puts "BUILDER: Creating Vivado simulation project part $part_name"
BUILDER: Creating Vivado simulation project part xc7k410tffg900-2
# create_project -part $part_name -force $project_name/$project_name
# foreach src_file $design_srcs {
# if [expr [file isdirectory $src_file] == 1] {
# puts "BUILDER: Expanding Directory : $src_file"
# set dir_contents [glob $src_file/*.*]
# append design_srcs " " $dir_contents
# }
# }
# foreach src_file $design_srcs {
# set src_ext [file extension $src_file ]
# if [expr [lsearch {.vhd .vhdl} $src_ext] >= 0] {
# puts "BUILDER: Adding VHDL : $src_file"
# read_vhdl $src_file
# } elseif [expr [lsearch {.v .vh} $src_ext] >= 0] {
# puts "BUILDER: Adding Verilog : $src_file"
# read_verilog $src_file
# } elseif [expr [lsearch {.sv .svh} $src_ext] >= 0] {
# puts "BUILDER: Adding SVerilog: $src_file"
# read_verilog -sv $src_file
# } elseif [expr [lsearch {.xdc} $src_ext] >= 0] {
# puts "BUILDER: Adding XDC : $src_file"
# read_xdc $src_file
# } elseif [expr [lsearch {.xci} $src_ext] >= 0] {
# puts "BUILDER: Adding IP : $src_file"
# read_ip $src_file
# } elseif [expr [lsearch {.ngc .edif} $src_ext] >= 0] {
# puts "BUILDER: Adding Netlist : $src_file"
# read_edif $src_file
# } elseif [expr [lsearch {.dat} $src_ext] >= 0] {
# puts "BUILDER: Adding Data File : $src_file"
# add_files -fileset $sim_fileset -norecurse $src_file
# } elseif [expr [lsearch {.bd} $src_ext] >= 0] {
# puts "BUILDER: Adding Block Diagram: $src_file"
# add_files -norecurse $src_file
# } elseif [expr [lsearch {.bxml} $src_ext] >= 0] {
# puts "BUILDER: Adding Block Diagram XML: $src_file"
# add_files -norecurse $src_file
# } else {
# puts "BUILDER: \[WARNING\] File ignored!!!: $src_file"
# }
# }
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_demux4.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_demux8.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_demux.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo16.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo16_to_fifo32.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_bram.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_cascade.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_short.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_filter_mux4.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_loopback.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_mux4.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_mux8.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_mux_select.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_mux.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_packet_gate.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/fifo64_to_axi4lite.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/shortfifo.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axis_fifo_monitor.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axis_strm_monitor.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk_sim.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_chdr_header_trigger.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_chdr_test_pattern.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_defs.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_dma_fifo.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_dma_master.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_embed_tlast.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_extract_tlast.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_fast_extract_tlast.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_embed_tlast_tkeep.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_extract_tlast_tkeep.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_fast_fifo.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_to_strobed.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_data_swap.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_dummy.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/strobed_to_axi.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_add_preamble.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axi_strip_preamble.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/crc_xnor.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_packet_flush.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_shift_register.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_upsizer.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_downsizer.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_width_conv.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_split.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_packetize.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/ad5662_auto_spi.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/arb_qualify_master.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/axi_crossbar.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/axi_crossbar_regport.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/axi_fifo_header.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/axi_forwarding_cam.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/axi_setting_reg.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/axi_slave_mux.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/axi_test_vfifo.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/bin2gray.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/binary_encoder.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/db_control.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/fe_control.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/filter_bad_sid.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/gearbox_2x1.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/gpio_atr_io.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/gpio_atr.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/gray2bin.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/por_gen.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/priority_encoder_one_hot.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/priority_encoder.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/ram_2port_impl.vh
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/ram_2port.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/reset_sync.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/s7_icap_wb.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/serial_to_settings.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/setting_reg.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/settings_bus_mux.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/settings_bus_timed_2clk.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/simple_i2c_core.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/simple_spi_core.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/simple_spi_core_64bit.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/synchronizer_impl.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/synchronizer.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/pulse_synchronizer.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/user_settings.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/axil_regport_master.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/axil_to_ni_regport.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/regport_resp_mux.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/regport_to_xbar_settingsbus.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/regport_to_settingsbus.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/pulse_stretch.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/pulse_stretch_min.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/mdio_master.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/map/cam_bram.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/map/cam_srl.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/map/cam.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/map/kv_map.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/map/axis_muxed_kv_map.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/axil_ctrlport_master.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/handshake.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/ctrlport_to_regport.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/glitch_free_mux.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/timing/time_compare.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/timing/timekeeper_legacy.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/timing/pps_generator.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/timing/pps_synchronizer.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/timing/pulse_generator.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/packet_proc/chdr_chunker.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/packet_proc/chdr_dechunker.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/packet_proc/cvita_dest_lookup.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/packet_proc/arm_deframer.v
BUILDER: Adding VHDL : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/packet_proc/arp_responder/arp_responder.vhd
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/acc.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/add2_and_clip_reg.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/add2_and_clip.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/add2_and_round_reg.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/add2_and_round.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/add2_reg.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/add2.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/add_then_mac.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/cic_decim.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/cic_dec_shifter.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/cic_interp.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/cic_int_shifter.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/cic_strober.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/clip_reg.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/clip.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/cordic_stage.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/cordic_z24.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/ddc_chain.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/duc_chain.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/hb47_int.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/hb_dec.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/hb_interp.v
BUILDER: [WARNING] File ignored!!!: /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/Makefile.srcs
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/mult_add_clip.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/round_reg.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/round_sd.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/round.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/rx_dcoffset.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/rx_frontend.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/sign_extend.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/small_hb_dec.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/small_hb_int.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/srl.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/tx_frontend.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/dsp/variable_delay_line.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/chdr_fifo_large.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/noc_shell_regs.vh
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_bit_reduce.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/null_source.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/split_stream.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/split_stream_fifo.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/conj.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/delay_fifo.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/delay_type2.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/delay_type3.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/delay_type4.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/complex_to_magsq.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/phase_accum.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/complex_invert.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/periodic_framer.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/moving_sum.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/counter.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/ram_to_fifo.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/const.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/const_sreg.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/cmul.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/cadd.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/keep_one_in_n.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/vector_iir.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/addsub.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_pipe.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/multiply.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/mult.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/mult_add.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/mult_rc.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/mult_add_rc.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fft_shift.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_pipe_join.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_pipe_mac.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_round_and_clip_complex.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_round_complex.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_clip_complex.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_join.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_sync.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/split_complex.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_round_and_clip.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/join_complex.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_round.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_clip.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_clip_unsigned.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_serializer.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_deserializer.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_packer.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/complex_to_mag_approx.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/file_source.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/delay.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/rng.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/f15_avg.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/f15_binmap.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/f15_core.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/f15_eoseq.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/f15_histo_mem.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/f15_line_mem.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/f15_logpwr.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/f15_maxhold.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/f15_packetizer.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/f15_rise_decay.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/f15_wf_agg.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fosphor/axi_logpwr.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/cvita_hdr_parser.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/cvita_hdr_encoder.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/cvita_hdr_decoder.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/cvita_hdr_modify.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_async_stream.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_rate_change.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_tag_time.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_drop_partial_packet.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/ddc.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/duc.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/cic_decimate.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/cic_interpolate.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/sine_tone.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_fir_filter.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/fir_filter_slice.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/axi_fir_filter_dec.v
BUILDER: Adding VHDL : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/addsub.vhd
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/dds_freq_tune.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/dds_freq_tune_duc.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/dds_timed.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/dds_wrapper.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/datapath_gatekeeper.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/axis_ctrl_endpoint.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/axis_ctrl_master.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/axis_ctrl_slave.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_compute_tkeep.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_to_chdr_data.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_pyld_ctxt.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_data.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_ingress_fifo.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_mgmt_pkt_handler.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_data_swapper.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_stream_endpoint.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_stream_input.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_stream_output.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_ctrl.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/ctrlport_endpoint.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/backend_iface.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/rfnoc_core_kernel.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/chdr_trim_payload.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/chdr_pad_packet.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/chdr_resize.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/chdr_convert_up.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/chdr_convert_down.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/context_handler_sync.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/context_builder.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/context_parser.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/ctrlport_timer.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/ctrlport_combiner.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/ctrlport_decoder.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/ctrlport_decoder_param.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/ctrlport_splitter.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/ctrlport_resp_combine.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/ctrlport_clk_cross.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/ctrlport_reg_rw.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/ctrlport_reg_ro.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/ctrlport_to_settings_bus.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/noc_shell_generic_ctrlport_pyld_chdr.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/timekeeper.v
BUILDER: Adding Verilog : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/utils/ctrlport_terminator.v
BUILDER: Adding Verilog : /home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/rfnoc_block_conv.v
BUILDER: Adding Verilog : /home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/noc_shell_conv.v
BUILDER: Adding IP : /home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/build-ip/xc7k410tffg900-2/axi_conv/axi_conv.xci
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
# foreach sim_src $sim_srcs {
# puts "BUILDER: Adding Sim Src : $sim_src"
# add_files -fileset $sim_fileset -norecurse $sim_src
# }
BUILDER: Adding Sim Src : /home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/rfnoc_block_conv_tb.sv
# foreach inc_src $inc_srcs {
# puts "BUILDER: Adding Inc Src : $inc_src"
# add_files -fileset $sim_fileset -norecurse $inc_src
# }
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/general/sim_clks_rsts.vh
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/general/sim_exec_report.vh
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/general/sim_math.vh
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/general/sim_file_io.svh
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/axi/sim_axi4_lib.svh
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/axi/sim_axis_lib.svh
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/axi/sim_cvita_lib.svh
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/control/sim_set_rb_lib.svh
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi4lite_sv/PkgAxiLite.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi4lite_sv/AxiLiteIf.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgTestExec.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/test_exec.svh
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/sim_clock_gen.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgAxiLiteBfm.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgEthernet.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgChdrData.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgChdrUtils.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgChdrBfm.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgAxisCtrlBfm.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgRfnocItemUtils.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgCtrlIfaceBfm.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgChdrIfaceBfm.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgRfnocBlockCtrlBfm.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/packages/PkgMath.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/packages/PkgComplex.sv
BUILDER: Adding Inc Src : /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/packages/PkgRandom.sv
# set_property top $sim_top [get_filesets $sim_fileset]
# set_property default_lib xil_defaultlib [current_project]
# update_compile_order -fileset sim_1 -quiet
# set_property target_simulator $simulator [current_project]
# if [expr [string equal $simulator "XSim"] == 1] {
# append verilog_defs " WORKING_DIR=\"$working_dir\""
# } else {
# append verilog_defs " WORKING_DIR=$working_dir"
# }
# set_property verilog_define $verilog_defs [get_filesets $sim_fileset]
# set_property xsim.simulate.runtime "${sim_runtime}us" -objects [get_filesets $sim_fileset]
# set_property xsim.elaborate.debug_level "all" -objects [get_filesets $sim_fileset]
# set_property xsim.elaborate.unifast $sim_fast -objects [get_filesets $sim_fileset]
# set_property xsim.elaborate.xelab.more_options -value {-timescale 1ns/1ns} -objects [get_filesets $sim_fileset]
# if [expr [string equal $simulator "Modelsim"] == 1] {
# set sim_64bit $::env(VIV_SIM_64BIT)
#
# set_property compxlib.modelsim_compiled_library_dir $sim_complibdir [current_project]
# # Does not work yet (as of Vivado 2015.2), but will be useful for 32-bit support
# # See: http://www.xilinx.com/support/answers/62210.html
# set_property modelsim.64bit $sim_64bit -objects [get_filesets $sim_fileset]
# set_property modelsim.simulate.runtime "${sim_runtime}ns" -objects [get_filesets $sim_fileset]
# set_property modelsim.elaborate.acc "true" -objects [get_filesets $sim_fileset]
# set_property modelsim.simulate.log_all_signals "true" -objects [get_filesets $sim_fileset]
# set_property modelsim.simulate.vsim.more_options -value "-c" -objects [get_filesets $sim_fileset]
# set_property modelsim.elaborate.unifast $sim_fast -objects [get_filesets $sim_fileset]
# if [info exists ::env(VIV_SIM_USER_DO) ] {
# set_property modelsim.simulate.custom_udo -value "$::env(VIV_SIM_USER_DO)" -objects [get_filesets $sim_fileset]
# }
# }
# launch_simulation
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/xsim_proj/xsim_proj.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/tools/Xilinx/Vivado/2019.1/data/xsim/xsim.ini' copied to run dir:'/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/xsim_proj/xsim_proj.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'rfnoc_block_conv_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/xsim_proj/xsim_proj.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj rfnoc_block_conv_tb_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_demux.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axi_demux
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axi_fifo
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk_sim.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axi_fifo_2clk
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_bram.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axi_fifo_bram
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axi_fifo_flop
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axi_fifo_flop2
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_short.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axi_fifo_short
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_mux.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axi_mux
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/fifo/axi_packet_gate.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axi_packet_gate
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/axis_ctrl_master.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_ctrl_master
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/axis_ctrl_slave.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_ctrl_slave
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_downsizer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_downsizer
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_packet_flush.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_packet_flush
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_pyld_ctxt_to_chdr
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_upsizer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_upsizer
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi/axis_width_conv.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_width_conv
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/backend_iface.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module backend_iface
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/bin2gray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bin2gray
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_compute_tkeep.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chdr_compute_tkeep
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_to_axis_pyld_ctxt.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chdr_to_axis_pyld_ctxt
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/ctrlport_endpoint.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ctrlport_endpoint
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/gray2bin.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gray2bin
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/noc_shell_conv.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module noc_shell_conv
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/pulse_stretch_min.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module pulse_stretch_min
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/pulse_synchronizer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module pulse_synchronizer
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/ram_2port.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ram_2port_impl_auto
INFO: [VRFC 10-311] analyzing module ram_2port_impl_reg
INFO: [VRFC 10-311] analyzing module ram_2port_impl_lutram
INFO: [VRFC 10-311] analyzing module ram_2port_impl_bram
INFO: [VRFC 10-311] analyzing module ram_2port_impl_uram
INFO: [VRFC 10-311] analyzing module ram_2port
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/rfnoc_block_conv.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module rfnoc_block_conv
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/synchronizer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module synchronizer
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/control/synchronizer_impl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module synchronizer_impl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgChdrData.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgChdrUtils.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgAxisCtrlBfm.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgChdrBfm.sv" into library xil_defaultlib
WARNING: [VRFC 10-674] expression with variable or undeterminable width as argument to $bits [/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgChdrBfm.sv:342]
WARNING: [VRFC 10-674] expression with variable or undeterminable width as argument to $bits [/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgChdrBfm.sv:379]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgChdrIfaceBfm.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgCtrlIfaceBfm.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgRfnocBlockCtrlBfm.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgRfnocItemUtils.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgTestExec.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/sim_clock_gen.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module sim_clock_gen
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/rfnoc_block_conv_tb.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module rfnoc_block_conv_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/xsim_proj/xsim_proj.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
xvhdl --incr --relax -prj rfnoc_block_conv_tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/build-ip/xc7k410tffg900-2/axi_conv/sim/axi_conv.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'axi_conv'
run_program: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1425.211 ; gain = 0.000 ; free physical = 2796 ; free virtual = 6710
INFO: [USF-XSim-69] 'compile' step finished in '6' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/xsim_proj/xsim_proj.sim/sim_1/behav/xsim'
xelab -wto d34fd6e25d494906a5b752b96fd37d28 --incr --debug all --relax --mt 8 -d UHD_FPGA_DIR=/home/wes/capstone/usrp/uhd/fpga/usrp3/top/../.. -d WORKING_DIR=/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L c_reg_fd_v12_0_6 -L c_gate_bit_v12_0_6 -L c_compare_v12_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_pipe_v3_0_6 -L xbip_dsp48_addsub_v3_0_6 -L xbip_addsub_v3_0_6 -L c_addsub_v12_0_13 -L xbip_counter_v3_0_6 -L c_counter_binary_v12_0_13 -L c_mux_bit_v12_0_6 -L c_mux_bus_v12_0_6 -L c_shift_ram_v12_0_13 -L convolution_v9_0_14 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot rfnoc_block_conv_tb_behav xil_defaultlib.rfnoc_block_conv_tb xil_defaultlib.glbl -log elaborate.log -timescale 1ns/1ns
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2019.1/bin/unwrapped/lnx64.o/xelab -wto d34fd6e25d494906a5b752b96fd37d28 --incr --debug all --relax --mt 8 -d UHD_FPGA_DIR=/home/wes/capstone/usrp/uhd/fpga/usrp3/top/../.. -d WORKING_DIR=/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L c_reg_fd_v12_0_6 -L c_gate_bit_v12_0_6 -L c_compare_v12_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_pipe_v3_0_6 -L xbip_dsp48_addsub_v3_0_6 -L xbip_addsub_v3_0_6 -L c_addsub_v12_0_13 -L xbip_counter_v3_0_6 -L c_counter_binary_v12_0_13 -L c_mux_bit_v12_0_6 -L c_mux_bus_v12_0_6 -L c_shift_ram_v12_0_13 -L convolution_v9_0_14 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot rfnoc_block_conv_tb_behav xil_defaultlib.rfnoc_block_conv_tb xil_defaultlib.glbl -log elaborate.log -timescale 1ns/1ns
Using 8 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 's_rfnoc_ctrl_tdata' [/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/rfnoc_block_conv_tb.sv:150]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'm_rfnoc_ctrl_tdata' [/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/rfnoc_block_conv_tb.sv:154]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 32 for port 's_rfnoc_ctrl_tdata' [/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/rfnoc_block_conv.v:153]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 32 for port 'm_rfnoc_ctrl_tdata' [/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/rfnoc_block_conv.v:158]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 32 for port 'm_in_payload_tdata' [/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/rfnoc_block_conv.v:182]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 32 for port 's_out_payload_tdata' [/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/rfnoc_block_conv.v:194]
WARNING: [VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 [/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv:245]
Completed static elaboration
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 245, File /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 245, File /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv
Starting simulation data flow analysis
WARNING: [XSIM 43-4328] File: /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgRfnocBlockCtrlBfm.sv Line: 183 : Sensitivity on input argument "port_num" of task "connect_master_data_port" may never get triggered.
WARNING: [XSIM 43-3980] File "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgRfnocBlockCtrlBfm.sv" Line 183 : The SystemVerilog feature ": Sensitivity on input argument of Class Member Task" is not supported yet for simulation.
WARNING: [XSIM 43-4328] File: /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgRfnocBlockCtrlBfm.sv Line: 199 : Sensitivity on input argument "port_num" of task "connect_slave_data_port" may never get triggered.
WARNING: [XSIM 43-3980] File "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgRfnocBlockCtrlBfm.sv" Line 199 : The SystemVerilog feature ": Sensitivity on input argument of Class Member Task" is not supported yet for simulation.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package convolution_v9_0_14.conv_ul_utils
Compiling package convolution_v9_0_14.conv_pkg
Compiling package convolution_v9_0_14.convolution_v9_0_14_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package c_mux_bus_v12_0_6.c_mux_bus_v12_0_6_viv_comp
Compiling package c_mux_bit_v12_0_6.c_mux_bit_v12_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package c_mux_bit_v12_0_6.c_mux_bit_v12_0_6_pkg
Compiling package c_reg_fd_v12_0_6.c_reg_fd_v12_0_6_viv_comp
Compiling package c_counter_binary_v12_0_13.c_counter_binary_v12_0_13_viv_co...
Compiling package xbip_counter_v3_0_6.xbip_counter_v3_0_6_viv_comp
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_counter_v3_0_6.xbip_counter_v3_0_6_pkg
Compiling package c_counter_binary_v12_0_13.c_counter_binary_v12_0_13_pkg
Compiling package c_addsub_v12_0_13.c_addsub_v12_0_13_pkg_legacy
Compiling package c_addsub_v12_0_13.c_addsub_v12_0_13_pkg
Compiling package c_compare_v12_0_6.c_compare_v12_0_6_viv_comp
Compiling package c_compare_v12_0_6.pkg_compare_v12_0
Compiling package c_gate_bit_v12_0_6.c_gate_bit_v12_0_6_viv_comp
Compiling package xil_defaultlib.PkgRfnocBlockCtrlBfm
Compiling package xil_defaultlib.PkgChdrUtils
Compiling package xil_defaultlib.PkgChdrData
Compiling package xil_defaultlib.PkgChdrBfm
Compiling package xil_defaultlib.PkgAxiStreamBfm
Compiling package std.std
Compiling package xil_defaultlib.PkgCtrlIfaceBfm
Compiling package xil_defaultlib.PkgAxisCtrlBfm
Compiling package xil_defaultlib.PkgChdrIfaceBfm
Compiling package xil_defaultlib.PkgTestExec
Compiling package xil_defaultlib.PkgRfnocItemUtils
Compiling package xil_defaultlib.$unit_AxiStreamIf_sv
Compiling module xil_defaultlib.RfnocBackendIf
Compiling module xil_defaultlib.AxiStreamIf(DATA_WIDTH=32)
Compiling module xil_defaultlib.AxiStreamIf_default
Compiling module xil_defaultlib.sim_clock_gen(PERIOD=5.0)
Compiling module xil_defaultlib.sim_clock_gen(PERIOD=25.0)
Compiling module xil_defaultlib.synchronizer_impl(WIDTH=33,INITI...
Compiling module xil_defaultlib.synchronizer(WIDTH=33,INITIAL_VA...
Compiling module xil_defaultlib.synchronizer_impl_default
Compiling module xil_defaultlib.synchronizer_default
Compiling module xil_defaultlib.pulse_synchronizer(MODE="POSEDGE...
Compiling module xil_defaultlib.pulse_stretch_min(LENGTH=32)
Compiling module xil_defaultlib.synchronizer_impl(WIDTH=2,INITIA...
Compiling module xil_defaultlib.synchronizer(WIDTH=2,INITIAL_VAL...
Compiling module xil_defaultlib.backend_iface(NOC_ID=32'b0100110...
Compiling module xil_defaultlib.synchronizer_impl(INITIAL_VAL=1'...
Compiling module xil_defaultlib.synchronizer(INITIAL_VAL=1'b1)
Compiling module xil_defaultlib.synchronizer_impl(WIDTH=5)
Compiling module xil_defaultlib.synchronizer(WIDTH=5)
Compiling module xil_defaultlib.bin2gray(WIDTH=5)
Compiling module xil_defaultlib.gray2bin(WIDTH=5)
Compiling module xil_defaultlib.axi_fifo_2clk(SIZE=1,WIDTH=33,PI...
Compiling module xil_defaultlib.axi_fifo_2clk(SIZE=1,WIDTH=33,PI...
Compiling module unisims_ver.SRLC32E_default
Compiling module xil_defaultlib.axi_fifo_short(WIDTH=33)
Compiling module xil_defaultlib.axi_fifo(WIDTH=33)
Compiling module xil_defaultlib.axi_fifo_flop2(WIDTH=67)
Compiling module xil_defaultlib.axis_upsizer(RATIO=2)
Compiling module xil_defaultlib.axis_downsizer(OUT_DATA_W=64,OUT...
Compiling module xil_defaultlib.axis_width_conv(WORD_W=32,IN_WOR...
Compiling module xil_defaultlib.ram_2port_impl_lutram(DWIDTH=67,...
Compiling module xil_defaultlib.ram_2port(DWIDTH=67,AWIDTH=4,RW_...
Compiling module xil_defaultlib.axi_fifo_flop2(WIDTH=4)
Compiling module xil_defaultlib.axi_fifo(WIDTH=4,SIZE=1)
Compiling module xil_defaultlib.axi_packet_gate(WIDTH=66,SIZE=4)
Compiling module xil_defaultlib.axis_upsizer(IN_DATA_W=64,IN_USE...
Compiling module xil_defaultlib.axis_downsizer(RATIO=2)
Compiling module xil_defaultlib.axis_width_conv(WORD_W=32,IN_WOR...
Compiling module xil_defaultlib.axis_ctrl_slave
Compiling module xil_defaultlib.ctrlport_endpoint(THIS_PORTID=10...
Compiling module xil_defaultlib.axi_fifo_flop2(WIDTH=65)
Compiling module xil_defaultlib.chdr_compute_tkeep(CHDR_W=64)
Compiling module xil_defaultlib.axi_fifo_flop2(WIDTH=69)
Compiling module xil_defaultlib.axi_fifo(WIDTH=69,SIZE=1)
Compiling module xil_defaultlib.axi_fifo(WIDTH=67,SIZE=1)
Compiling module xil_defaultlib.axis_width_conv(WORD_W=32,IN_WOR...
Compiling module xil_defaultlib.synchronizer_impl(WIDTH=4,INITIA...
Compiling module xil_defaultlib.synchronizer(WIDTH=4,INITIAL_VAL...
Compiling module xil_defaultlib.axi_fifo_2clk(SIZE=1,WIDTH=33)
Compiling module xil_defaultlib.axi_fifo_flop2(WIDTH=34)
Compiling module xil_defaultlib.axis_packet_flush(WIDTH=33,PIPEL...
Compiling module xil_defaultlib.axis_packet_flush(WIDTH=68,PIPEL...
Compiling module xil_defaultlib.chdr_to_axis_pyld_ctxt(CHDR_W=64...
Compiling module xil_defaultlib.axis_width_conv(WORD_W=32,IN_WOR...
Compiling module xil_defaultlib.axi_fifo(WIDTH=65,SIZE=1)
Compiling module xil_defaultlib.axi_fifo_flop2(WIDTH=66)
Compiling module xil_defaultlib.axis_packet_flush(WIDTH=65,PIPEL...
Compiling module xil_defaultlib.ram_2port_impl_auto(DWIDTH=65,AW...
Compiling module xil_defaultlib.ram_2port(DWIDTH=65,AWIDTH=6'b01...
Compiling module xil_defaultlib.axi_fifo_flop2(WIDTH=6'b01101)
Compiling module xil_defaultlib.axi_fifo(WIDTH=6'b01101,SIZE=32'...
Compiling module xil_defaultlib.axi_fifo(WIDTH=6'b01101,SIZE=1)
Compiling module xil_defaultlib.axi_packet_gate(SIZE=6'b01101)
Compiling module xil_defaultlib.axis_pyld_ctxt_to_chdr(CHDR_W=64...
Compiling module xil_defaultlib.noc_shell_conv(THIS_PORTID=10'b0...
Compiling architecture xilinx of entity axi_utils_v2_0_6.glb_srl_fifo [\glb_srl_fifo(width=2,has_uvprot...]
Compiling architecture xilinx of entity axi_utils_v2_0_6.glb_ifx_master [\glb_ifx_master(width=2,afull_th...]
Compiling architecture synth of entity convolution_v9_0_14.conv_reg [\conv_reg(c_width=2,c_has_ce=1,c...]
Compiling architecture struct of entity c_compare_v12_0_6.c_compare_eq_ne [\c_compare_eq_ne(c_family="kinte...]
Compiling architecture synth of entity c_compare_v12_0_6.c_compare_v12_0_6_viv [\c_compare_v12_0_6_viv(c_family=...]
Compiling architecture synth of entity convolution_v9_0_14.conv_compare [\conv_compare(c_family="kintex7"...]
Compiling architecture structural of entity c_reg_fd_v12_0_6.c_reg_fd_v12_0_6_viv [\c_reg_fd_v12_0_6_viv(c_width=2,...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity c_addsub_v12_0_13.c_addsub_v12_0_13_lut6_legacy [\c_addsub_v12_0_13_lut6_legacy(c...]
Compiling architecture synth of entity c_addsub_v12_0_13.c_addsub_v12_0_13_fabric_legacy [\c_addsub_v12_0_13_fabric_legacy...]
Compiling architecture synth of entity c_addsub_v12_0_13.c_addsub_v12_0_13_legacy [\c_addsub_v12_0_13_legacy(c_fami...]
Compiling architecture synth of entity c_counter_binary_v12_0_13.c_counter_binary_v12_0_13_legacy [\c_counter_binary_v12_0_13_legac...]
Compiling architecture synth of entity c_counter_binary_v12_0_13.c_counter_binary_v12_0_13_viv [\c_counter_binary_v12_0_13_viv(c...]
Compiling architecture synth of entity convolution_v9_0_14.conv_counter_binary [\conv_counter_binary(c_width=2,c...]
Compiling architecture synth of entity convolution_v9_0_14.conv_countera [\conv_countera(c_width=2,c_count...]
Compiling architecture synth of entity convolution_v9_0_14.conv_bit_reg [\conv_bit_reg(c_has_ce=1,c_has_a...]
Compiling architecture structural of entity c_reg_fd_v12_0_6.c_reg_fd_v12_0_6_viv [\c_reg_fd_v12_0_6_viv(c_sync_pri...]
Compiling architecture struct of entity c_mux_bit_v12_0_6.c_mux_bit_pipereg [\c_mux_bit_pipereg(c_mux_inputs=...]
Compiling architecture synth of entity c_mux_bit_v12_0_6.c_mux_bit_v12_0_6_viv [\c_mux_bit_v12_0_6_viv(c_family=...]
Compiling architecture rtl of entity c_mux_bus_v12_0_6.c_mux_bus_v12_0_6_viv [\c_mux_bus_v12_0_6_viv(c_family=...]
Compiling architecture synth of entity convolution_v9_0_14.conv_mux_bus [\conv_mux_bus(c_width=3,c_s_widt...]
Compiling architecture synth of entity convolution_v9_0_14.conv_mux2_bus [\conv_mux2_bus(c_width=3,c_has_a...]
Compiling architecture synth of entity convolution_v9_0_14.punc [\punc(c_punc_input_rate=2,punctu...]
Compiling architecture synth of entity convolution_v9_0_14.conv_reg [\conv_reg(c_width=7,c_has_ce=1,c...]
Compiling architecture synth of entity convolution_v9_0_14.convolution_v9_0_14_main [\convolution_v9_0_14_main(c_outp...]
Compiling architecture synth of entity convolution_v9_0_14.convolution_axi_wrapper [\convolution_axi_wrapper(c_has_m...]
Compiling architecture synth of entity convolution_v9_0_14.convolution_v9_0_14_viv [\convolution_v9_0_14_viv(c_has_m...]
Compiling architecture xilinx of entity convolution_v9_0_14.convolution_v9_0_14 [\convolution_v9_0_14(c_has_m_axi...]
Compiling architecture axi_conv_arch of entity xil_defaultlib.axi_conv [axi_conv_default]
Compiling module xil_defaultlib.rfnoc_block_conv(THIS_PORTID=10'...
Compiling module xil_defaultlib.rfnoc_block_conv_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot rfnoc_block_conv_tb_behav
****** Webtalk v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
**** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source /home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/xsim_proj/xsim_proj.sim/sim_1/behav/xsim/xsim.dir/rfnoc_block_conv_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/xsim_proj/xsim_proj.sim/sim_1/behav/xsim/xsim.dir/rfnoc_block_conv_tb_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Wed May 11 02:17:46 2022. For additional details about this file, please refer to the WebTalk help file at /tools/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Wed May 11 02:17:46 2022...
run_program: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1425.211 ; gain = 0.000 ; free physical = 2791 ; free virtual = 6709
INFO: [USF-XSim-69] 'elaborate' step finished in '19' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/wes/capstone/oot_modules/rfnoc_blocks/rfnoc-convolution/rfnoc/fpga/rfnoc_block_conv/xsim_proj/xsim_proj.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "rfnoc_block_conv_tb_behav -key {Behavioral:sim_1:Functional:rfnoc_block_conv_tb} -tclbatch {rfnoc_block_conv_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source rfnoc_block_conv_tb.tcl
## current_wave_config
WARNING: Simulation object /rfnoc_block_conv_tb/blk_ctrl was not traceable in the design for the following reason:
Vivado Simulator does not support tracing of System Verilog Dynamic Type object.
========================================================
TESTBENCH STARTED: rfnoc_block_conv_tb
========================================================
[TEST CASE 1] (t = 0 ns) BEGIN: Flush block then reset it...
[TEST CASE 1] (t = 6450 ns) DONE... Passed
[TEST CASE 2] (t = 6450 ns) BEGIN: Verify Block Info...
[TEST CASE 2] (t = 6450 ns) DONE... Passed
[TEST CASE 3] (t = 6450 ns) BEGIN: Test passing through samples...
Fatal: Timeout: Test "Test passing through samples" time limit exceeded
Time: 16450 ns Iteration: 0 Process: /PkgTestExec/TestExec::start_timeout/Block260_9/timeout File: /home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgTestExec.sv
$finish called at time : 16450 ns : File "/home/wes/capstone/usrp/uhd/fpga/usrp3/sim/rfnoc/PkgTestExec.sv" Line 235
INFO: [USF-XSim-96] XSim completed. Design snapshot 'rfnoc_block_conv_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000000000us
launch_simulation: Time (s): cpu = 00:00:38 ; elapsed = 00:00:43 . Memory (MB): peak = 1458.008 ; gain = 42.445 ; free physical = 2785 ; free virtual = 6703
# if { [info exists ::env(VIV_SYNTH_TOP)] } {
# puts "BUILDER: Synthesizing"
# # Synthesize requested modules
# foreach synth_top "$::env(VIV_SYNTH_TOP)" {
# set_property top $synth_top [current_fileset]
# synth_design -mode out_of_context
# # Perform a simple regex-based search for all clock signals and constrain
# # them to 500 MHz for the timing report.
# set clk_regexp "(?i)^(?!.*en.*).*(clk|clock).*"
# foreach clk_inst [get_ports -regexp $clk_regexp] {
# create_clock -name $clk_inst -period 2.0 [get_ports $clk_inst]
# }
# report_utilization -no_primitives -file ${working_dir}/${synth_top}_synth.rpt
# report_timing_summary -setup -max_paths 3 -unique_pins -no_header -append -file ${working_dir}/${synth_top}_synth.rpt
# write_checkpoint -force ${working_dir}/${synth_top}_synth.dcp
# }
# } else {
# puts "BUILDER: Skipping resource report because VIV_SYNTH_TOP is not set"
# }
BUILDER: Synthesizing
# if [string equal $vivado_mode "batch"] {
# puts "BUILDER: Closing project"
# close_project
# } else {
# puts "BUILDER: In GUI mode. Leaving project open."
# }
BUILDER: Closing project
INFO: [Common 17-206] Exiting Vivado at Wed May 11 02:17:55 2022...
//
// Copyright 2022 <+YOU OR YOUR COMPANY+>.
//
// This is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// This software is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this software; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
//
// Module: rfnoc_block_conv_tb
//
// Description: Testbench for the conv RFNoC block.
//
`default_nettype none
module rfnoc_block_conv_tb;
`include "test_exec.svh"
import PkgTestExec::*;
import PkgChdrUtils::*;
import PkgRfnocBlockCtrlBfm::*;
import PkgRfnocItemUtils::*;
//---------------------------------------------------------------------------
// Testbench Configuration
//---------------------------------------------------------------------------
localparam [ 9:0] THIS_PORTID = 10'h123;
localparam [31:0] NOC_ID = 32'h1337;
localparam int CHDR_W = 64;
localparam int ITEM_W = 8;
localparam int NUM_PORTS_I = 1;
localparam int NUM_PORTS_O = 1;
localparam int MTU = 13;
localparam int SPP = 64; // Samples per packet
localparam int PKT_SIZE_BYTES = SPP * (ITEM_W/8);
localparam int STALL_PROB = 25; // Default BFM stall probability
localparam real CHDR_CLK_PER = 5.0; // Clock rate (200 MHz)
localparam real CTRL_CLK_PER = 25.0; // 40 MHz
//---------------------------------------------------------------------------
// Clocks and Resets
//---------------------------------------------------------------------------
bit rfnoc_chdr_clk;
bit rfnoc_ctrl_clk;
sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
sim_clock_gen #(CTRL_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
//---------------------------------------------------------------------------
// Bus Functional Models
//---------------------------------------------------------------------------
// Backend Interface
RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_ctrl_clk);
// AXIS-Ctrl Interface
AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, 1'b0);
AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, 1'b0);
// AXIS-CHDR Interfaces
AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS_I] (rfnoc_chdr_clk, 1'b0);
AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS_O] (rfnoc_chdr_clk, 1'b0);
// Block Controller BFM
RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);
// CHDR word and item/sample data types
typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t;
// Connect block controller to BFMs
for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_bfm_input_connections
initial begin
blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
blk_ctrl.set_master_stall_prob(i, STALL_PROB);
end
end
for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_bfm_output_connections
initial begin
blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
end
end
//---------------------------------------------------------------------------
// Device Under Test (DUT)
//---------------------------------------------------------------------------
// DUT Slave (Input) Port Signals
logic [CHDR_W*NUM_PORTS_I-1:0] s_rfnoc_chdr_tdata;
logic [ NUM_PORTS_I-1:0] s_rfnoc_chdr_tlast;
logic [ NUM_PORTS_I-1:0] s_rfnoc_chdr_tvalid;
logic [ NUM_PORTS_I-1:0] s_rfnoc_chdr_tready;
// DUT Master (Output) Port Signals
logic [CHDR_W*NUM_PORTS_O-1:0] m_rfnoc_chdr_tdata;
logic [ NUM_PORTS_O-1:0] m_rfnoc_chdr_tlast;
logic [ NUM_PORTS_O-1:0] m_rfnoc_chdr_tvalid;
logic [ NUM_PORTS_O-1:0] m_rfnoc_chdr_tready;
// Map the array of BFMs to a flat vector for the DUT connections
for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_dut_input_connections
// Connect BFM master to DUT slave port
assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
assign s_rfnoc_chdr_tlast[i] = m_chdr[i].tlast;
assign s_rfnoc_chdr_tvalid[i] = m_chdr[i].tvalid;
assign m_chdr[i].tready = s_rfnoc_chdr_tready[i];
end
for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_dut_output_connections
// Connect BFM slave to DUT master port
assign s_chdr[i].tdata = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
assign s_chdr[i].tlast = m_rfnoc_chdr_tlast[i];
assign s_chdr[i].tvalid = m_rfnoc_chdr_tvalid[i];
assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
end
rfnoc_block_conv #(
.THIS_PORTID (THIS_PORTID),
.CHDR_W (CHDR_W),
.MTU (MTU)
) dut (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_core_config (backend.cfg),
.rfnoc_core_status (backend.sts),
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
.s_rfnoc_ctrl_tdata (m_ctrl.tdata),
.s_rfnoc_ctrl_tlast (m_ctrl.tlast),
.s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
.s_rfnoc_ctrl_tready (m_ctrl.tready),
.m_rfnoc_ctrl_tdata (s_ctrl.tdata),
.m_rfnoc_ctrl_tlast (s_ctrl.tlast),
.m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
.m_rfnoc_ctrl_tready (s_ctrl.tready)
);
//---------------------------------------------------------------------------
// Main Test Process
//---------------------------------------------------------------------------
initial begin : tb_main
// Initialize the test exec object for this testbench
test.start_tb("rfnoc_block_conv_tb");
// Start the BFMs running
blk_ctrl.run();
//--------------------------------
// Reset
//--------------------------------
test.start_test("Flush block then reset it", 10us);
blk_ctrl.flush_and_reset();
test.end_test();
//--------------------------------
// Verify Block Info
//--------------------------------
test.start_test("Verify Block Info", 2us);
`ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
test.end_test();
//--------------------------------
// Test Sequences
//--------------------------------
// begin
// Read and write the user register to make sure it updates correctly.
// logic [7:0] write_val, read_val;
// test.start_test("Verify user register", 5us);
// Test user register has a default value
// blk_ctrl.reg_read(dut.REG_USER_ADDR, read_val);
// `ASSERT_ERROR(
// read_val == dut.REG_USER_DEFAULT, "Incorrect default value for user register");
// Test writing and read user register works
// write_val = $random();
// blk_ctrl.reg_write(dut.REG_USER_ADDR, write_val);
// blk_ctrl.reg_read(dut.REG_USER_ADDR, read_val);
// `ASSERT_ERROR(
// read_val == write_val, "Initial value for user register is incorrect");
// test.end_test();
// end
begin
int num_bytes;
item_t send_samples[$];
item_t recv_samples[$];
item_t gnd_truth_samples[$];
test.start_test("Test passing through samples", 10us);
// Generate a payload of random samples
send_samples = {57, 95, 22, 163, 46};
for (int i = 0; i < 5; i++) begin
send_samples.push_back($random()); // 8-bit samples
end
// Queue a packet for transfer
blk_ctrl.send_items(0, send_samples);
// Receive the output packet
blk_ctrl.recv_items(0, recv_samples);
// Check the resulting payload size
`ASSERT_ERROR(recv_samples.size() == 15,
"Received payload didn't match size of payload sent");
// Ground truth data to compare
gnd_truth_samples = {3, 234, 159, 48, 205, 109, 76, 115, 50, 134, 22, 62, 79, 153, 170};
// Check the resulting samples
for (int i = 0; i < 15; i++) begin
item_t sample_gnd_truth;
item_t sample_out;
sample_gnd_truth = gnd_truth_samples[i];
sample_out = recv_samples[i];
`ASSERT_ERROR(
sample_out == sample_gnd_truth,
$sformatf("Sample %4d, received 0x%08X, expected 0x%08X",
i, sample_out, sample_gnd_truth));
end
test.end_test();
end
//--------------------------------
// Finish Up
//--------------------------------
// Display final statistics and results
test.end_tb();
end : tb_main
endmodule : rfnoc_block_conv_tb
`default_nettype wire
//
// Copyright 2022 <+YOU OR YOUR COMPANY+>.
//
// This is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// This software is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this software; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
//
// Module: rfnoc_block_conv
//
// Description:
//
// This is a skeleton file for a RFNoC block. It passes incoming samples
// to the output without any modification. A read/write user register is
// instantiated, but left unused.
//
// Parameters:
//
// THIS_PORTID : Control crossbar port to which this block is connected
// CHDR_W : AXIS-CHDR data bus width
// MTU : Maximum transmission unit (i.e., maximum packet size in
// CHDR words is 2**MTU).
//
`default_nettype none
module rfnoc_block_conv #(
parameter [9:0] THIS_PORTID = 10'd0,
parameter CHDR_W = 64,
parameter [5:0] MTU = 10,
parameter NUM_PORTS = 1
)(
// RFNoC Framework Clocks and Resets
input wire rfnoc_chdr_clk,
input wire rfnoc_ctrl_clk,
input wire ce_clk,
// RFNoC Backend Interface
input wire [511:0] rfnoc_core_config,
output wire [511:0] rfnoc_core_status,
// AXIS-CHDR Input Ports (from framework)
input wire [(1)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
input wire [(1)-1:0] s_rfnoc_chdr_tlast,
input wire [(1)-1:0] s_rfnoc_chdr_tvalid,
output wire [(1)-1:0] s_rfnoc_chdr_tready,
// AXIS-CHDR Output Ports (to framework)
output wire [(1)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
output wire [(1)-1:0] m_rfnoc_chdr_tlast,
output wire [(1)-1:0] m_rfnoc_chdr_tvalid,
input wire [(1)-1:0] m_rfnoc_chdr_tready,
// AXIS-Ctrl Input Port (from framework)
input wire [7:0] s_rfnoc_ctrl_tdata,
input wire s_rfnoc_ctrl_tlast,
input wire s_rfnoc_ctrl_tvalid,
output wire s_rfnoc_ctrl_tready,
// AXIS-Ctrl Output Port (to framework)
output wire [7:0] m_rfnoc_ctrl_tdata,
output wire m_rfnoc_ctrl_tlast,
output wire m_rfnoc_ctrl_tvalid,
input wire m_rfnoc_ctrl_tready
);
`include "/home/wes/capstone/usrp/uhd/fpga/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh"
//---------------------------------------------------------------------------
// Signal Declarations
//---------------------------------------------------------------------------
// Clocks and Resets
wire ctrlport_clk;
wire ctrlport_rst;
wire axis_data_clk;
wire axis_data_rst;
// CtrlPort Master
wire m_ctrlport_req_wr;
wire m_ctrlport_req_rd;
wire [19:0] m_ctrlport_req_addr;
wire [31:0] m_ctrlport_req_data;
reg m_ctrlport_resp_ack;
reg [31:0] m_ctrlport_resp_data;
// Payload Stream to User Logic: in
wire [8*1-1:0] m_in_payload_tdata;
wire [1-1:0] m_in_payload_tkeep;
wire [1-1:0] m_in_payload_tlast;
wire [1-1:0] m_in_payload_tvalid;
wire [1-1:0] m_in_payload_tready;
// Context Stream to User Logic: in
wire [CHDR_W-1:0] m_in_context_tdata;
wire [3:0] m_in_context_tuser;
wire [1-1:0] m_in_context_tlast;
wire [1-1:0] m_in_context_tvalid;
reg [1-1:0] m_in_context_tready;
// Payload Stream from User Logic: out
wire [8*1-1:0] s_out_payload_tdata;
wire [0:0] s_out_payload_tkeep;
wire [1-1:0] s_out_payload_tlast;
wire [1-1:0] s_out_payload_tvalid;
wire [1-1:0] s_out_payload_tready;
// Context Stream from User Logic: out
reg [CHDR_W-1:0] s_out_context_tdata;
reg [3:0] s_out_context_tuser;
reg [1-1:0] s_out_context_tlast;
reg [1-1:0] s_out_context_tvalid;
wire [1-1:0] s_out_context_tready;
wire ce_rst;
//---------------------------------------------------------------------------
// NoC Shell
//---------------------------------------------------------------------------
noc_shell_conv #(
.CHDR_W (CHDR_W),
.THIS_PORTID (THIS_PORTID),
.MTU (MTU)
) noc_shell_conv_i (
//---------------------
// Framework Interface
//---------------------
// Clock Inputs
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
// Reset Outputs
.rfnoc_chdr_rst (),
.rfnoc_ctrl_rst (),
// RFNoC Backend Interface
.rfnoc_core_config (rfnoc_core_config),
.rfnoc_core_status (rfnoc_core_status),
// CHDR Input Ports (from framework)
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
// CHDR Output Ports (to framework)
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
// AXIS-Ctrl Input Port (from framework)
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
// AXIS-Ctrl Output Port (to framework)
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
//---------------------
// Client Interface
//---------------------
// CtrlPort Clock and Reset
.ctrlport_clk (ce_clk),
.ctrlport_rst (ce_rst),
// CtrlPort Master
.m_ctrlport_req_wr (m_ctrlport_req_wr),
.m_ctrlport_req_rd (m_ctrlport_req_rd),
.m_ctrlport_req_addr (m_ctrlport_req_addr),
.m_ctrlport_req_data (m_ctrlport_req_data),
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
.m_ctrlport_resp_data (m_ctrlport_resp_data),
// AXI-Stream Payload Context Clock and Reset
.axis_data_clk (axis_data_clk),
.axis_data_rst (axis_data_rst),
// Payload Stream to User Logic: in
.m_in_payload_tdata (m_in_payload_tdata),
.m_in_payload_tkeep (m_in_payload_tkeep),
.m_in_payload_tlast (m_in_payload_tlast),
.m_in_payload_tvalid (m_in_payload_tvalid),
.m_in_payload_tready (m_in_payload_tready),
// Context Stream to User Logic: in
.m_in_context_tdata (m_in_context_tdata),
.m_in_context_tuser (m_in_context_tuser),
.m_in_context_tlast (m_in_context_tlast),
.m_in_context_tvalid (m_in_context_tvalid),
.m_in_context_tready (m_in_context_tready),
// Payload Stream from User Logic: out
.s_out_payload_tdata (s_out_payload_tdata),
.s_out_payload_tkeep (s_out_payload_tkeep),
.s_out_payload_tlast (s_out_payload_tlast),
.s_out_payload_tvalid (s_out_payload_tvalid),
.s_out_payload_tready (s_out_payload_tready),
// Context Stream from User Logic: out
.s_out_context_tdata (s_out_context_tdata),
.s_out_context_tuser (s_out_context_tuser),
.s_out_context_tlast (s_out_context_tlast),
.s_out_context_tvalid (s_out_context_tvalid),
.s_out_context_tready (s_out_context_tready)
);
//---------------------------------------------------------------------------
// User Registers
//---------------------------------------------------------------------------
//
// There's only one register now, but we'll structure the register code to
// make it easier to add more registers later.
// Register use the ctrlport_clk clock.
//
//---------------------------------------------------------------------------
// Note: Register addresses increment by 4
localparam REG_USER_ADDR = 0; // Address for example user register
localparam REG_USER_DEFAULT = 0; // Default value for user register
reg [31:0] reg_user = REG_USER_DEFAULT;
always @(posedge ctrlport_clk) begin
if (ctrlport_rst) begin
reg_user = REG_USER_DEFAULT;
end else begin
// Default assignment
m_ctrlport_resp_ack <= 0;
// Read user register
if (m_ctrlport_req_rd) begin // Read request
case (m_ctrlport_req_addr)
REG_USER_ADDR: begin
m_ctrlport_resp_ack <= 1;
m_ctrlport_resp_data <= reg_user;
end
endcase
end
// Write user register
if (m_ctrlport_req_wr) begin // Write requst
case (m_ctrlport_req_addr)
REG_USER_ADDR: begin
m_ctrlport_resp_ack <= 1;
reg_user <= m_ctrlport_req_data[31:0];
end
endcase
end
end
end
//---------------------------------------------------------------------------
// User Logic
//---------------------------------------------------------------------------
//
// User logic uses the axis_data_clk clock. While the registers above use the
// ctrlport_clk clock, in the block YAML configuration file both the control
// and data interfaces are specified to use the rfnoc_chdr clock. Therefore,
// we do not need to cross clock domains when using user registers with
// user logic.
//
//---------------------------------------------------------------------------
// Instantiate Xilinx Convolutional Encoder IP core and make AXI I/O connections
axi_conv inst_axi_conv (
.aclk(rfnoc_chdr_clk), .aresetn(~(ce_rst)),
.s_axis_data_tvalid(m_in_payload_tvalid),
.s_axis_data_tready(m_in_payload_tready),
.s_axis_data_tdata(m_in_payload_tdata[7:0]),
.m_axis_data_tvalid(s_out_payload_tvalid),
.m_axis_data_tready(s_out_payload_tready),
.m_axis_data_tdata(s_out_payload_tdata[7:0]));
// Pins not present on IP core; passing through unchanged
assign s_out_payload_tlast = m_in_payload_tlast;
//---------------------------------------------------------------------------
// Context Handling
//---------------------------------------------------------------------------
//
// Output packets have two thirds the payload size of input packets, so we
// need to update the header length field as it passes through.
//
//---------------------------------------------------------------------------
genvar port;
for (port = 0; port < NUM_PORTS; port = port+1) begin : gen_context_ports
always @(*) begin : update_packet_length
reg [CHDR_W-1:0] old_tdata;
reg [CHDR_W-1:0] new_tdata;
old_tdata = m_in_context_tdata[CHDR_W*port +: CHDR_W];
// Check if this context word contains the header
if (m_in_context_tuser[4*port +: 4] == CONTEXT_FIELD_HDR ||
m_in_context_tuser[4*port +: 4] == CONTEXT_FIELD_HDR_TS
) begin : change_header
// Update the lower 64-bits (the header word) with the new length
reg [15:0] pyld_length;
pyld_length = chdr_calc_payload_length(CHDR_W, old_tdata)*2 / 3;
new_tdata = old_tdata;
new_tdata[63:0] = chdr_update_length(CHDR_W, old_tdata, pyld_length);
end else begin : pass_through_header
// Not a header word, so pass through unchanged
new_tdata = old_tdata;
end
s_out_context_tdata [CHDR_W*port +: CHDR_W] = new_tdata;
s_out_context_tuser [ 4*port +: 4] = m_in_context_tuser [4*port +: 4];
s_out_context_tlast [ 1*port +: 1] = m_in_context_tlast [1*port +: 1];
s_out_context_tvalid [ 1*port +: 1] = m_in_context_tvalid [1*port +: 1];
m_in_context_tready [ 1*port +: 1] = s_out_context_tready [1*port +: 1];
end // update_packet_length
end // gen_context_ports
// Only 1-sample per clock, so tkeep should always be asserted
assign s_out_payload_tkeep = 1'b1;
endmodule // rfnoc_block_conv
`default_nettype wire
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