On 2022-05-26 10:31, [email protected] wrote:
Hi all!
I am starting to look through some of the FPGA code of the USRP X300
in order to understand which is the DDC chain configuration in the
default image.
I have understood that in the DDC chain there is 1 CIC filter + 3
Halfband filters. Since I want to characterize the DDC chain I have
the following questions:
1.
How are they used? I suppose that the halfband filters are used
based on the decimation factor we need (max. 1024)
2.
Which is the order of the CIC filter?
3.
How many taps each halfband filters have? Which are the taps?
Thank you in advance,
Luca
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Also:
uhd/fpga-src/usrp3/lib/dsp/hb_dec.v
Appears to have some coefficient settings.
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