If you prefer the coefficients in decimal, they are pulled from this file for the first and second stage:
https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x300/coregen_dsp/hb47.coe And this file for the third stage: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x300/coregen_dsp/hb63.coe Those COE files are referenced in the CoreGen IP files for these filters. You can see all the IP settings here: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xco https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xco https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xco Wade On Thu, May 26, 2022 at 10:22 AM Brian Padalino <bpadal...@gmail.com> wrote: > On Thu, May 26, 2022 at 10:43 AM <luca.vi...@argotecgroup.com> wrote: > >> Hi all! >> >> >> I am starting to look through some of the FPGA code of the USRP X300 in >> order to understand which is the DDC chain configuration in the default >> image. >> >> >> I have understood that in the DDC chain there is 1 CIC filter + 3 >> Halfband filters. Since I want to characterize the DDC chain I have the >> following questions: >> >> 1. >> >> How are they used? I suppose that the halfband filters are used based >> on the decimation factor we need (max. 1024) >> 2. >> >> Which is the order of the CIC filter? >> 3. >> >> How many taps each halfband filters have? Which are the taps? >> >> > Taking a look at the ddc.v file is the best insight. The cic_decimate has > an N which is the order it's given: > > > https://github.com/EttusResearch/uhd/blob/5333d3d12ffc21229ec4203a9ea1c7f68d82e57f/fpga/usrp3/lib/rfnoc/ddc.v#L283 > > Here it's listed as 4. > > In general, the CIC is used for bulk decimation up to 2, 4, or 8x > oversampled - ideally 8x. The hbdec1 is the first, hbdec2 is the next, and > hbdec3 is the last. Their coefficients can be found here: > > > https://github.com/EttusResearch/uhd/blob/5333d3d12ffc21229ec4203a9ea1c7f68d82e57f/fpga/usrp3/top/x300/coregen_dsp/hbdec1.mif > > https://github.com/EttusResearch/uhd/blob/5333d3d12ffc21229ec4203a9ea1c7f68d82e57f/fpga/usrp3/top/x300/coregen_dsp/hbdec2.mif > > https://github.com/EttusResearch/uhd/blob/5333d3d12ffc21229ec4203a9ea1c7f68d82e57f/fpga/usrp3/top/x300/coregen_dsp/hbdec3.mif > > If the desired decimation rate is divisible by 8, then all 3 halfbands are > used. If not, a division by 4 is checked, and 2 are used. If not, a > division by 2 is checked and 1 is used. If not, only the CIC is used. > > If you want to test your model against the HDL itself, a testbench is > located here: > > > https://github.com/EttusResearch/uhd/blob/5333d3d12ffc21229ec4203a9ea1c7f68d82e57f/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv > > But it's probably easier and much faster to pass samples through the > actual RFNoC block in a custom graph that just exercises the DDC. > > Brian > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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