Hi Yan, I received an email from Wade Fife at Ettus that mentioned a problem trying to build an RFNoC image with 2 radios and 2 replay blocks (without DUC/DDC) on E31x devices because of the relatively small FPGA. However, I later built an image using static links rather than dynamic links (see attached yml). This was built and runs on UHD 4.2. Rob
On Wed, Dec 7, 2022 at 3:57 PM <[email protected]> wrote: > Hi, All, > > I am currently trying to use the replay block with E312. Following the > instructions in this link: > https://kb.ettus.com/Using_the_RFNoC_Replay_Block_in_UHD_4 > > I have installed the vivado ML version and the corresponding patch for > E312 device. > > The “yml“ file is changed as in the following: > > # General parameters > > # ----------------------------------------- > > schema: rfnoc_imagebuilder_args # Identifier for the schema used to > validate this file > > copyright: >- # Copyright information used in file headers > > Ettus Research, A National Instruments Brand > > license: >- # License information used in file headers > > SPDX-License-Identifier: LGPL-3.0-or-later > > version: '1.0' # File version > > chdr_width: 64 # Bit width of the CHDR bus for this image > > device: 'e310' # USRP type > > image_core_name: 'e310' # Name to use for the RFNoC Image Core files > > default_target: 'E310_SG3' > > # A list of all stream endpoints in design > > # ---------------------------------------- > > stream_endpoints: > > ep0: # Stream endpoint name > > ctrl: True # Endpoint passes control traffic > > data: True # Endpoint passes data traffic > > buff_size: 16384 # Ingress buffer size for data > > ep1: > > ctrl: False > > data: True > > buff_size: 16384 > > # add relay block > > ep4: # Stream endpoint name > > ctrl: False # Endpoint passes control traffic > > data: True # Endpoint passes data traffic > > buff_size: 4096 # Ingress buffer size for data > > ep5: # Stream endpoint name > > ctrl: False # Endpoint passes control traffic > > data: True # Endpoint passes data traffic > > buff_size: 4096 # Ingress buffer size for data > > # A list of all NoC blocks in design > > # ---------------------------------- > > noc_blocks: > > radio0: # NoC block name > > block_desc: 'radio.yml' # Block device descriptor > > parameters: > > NUM_PORTS: 2 > > # add relay block > > replay0: > > block_desc: 'replay.yml' > > parameters: > > NUM_PORTS: 2 > > MEM_ADDR_W: 29 > > # A list of all static connections in design > > # ------------------------------------------ > > # Format: A list of connection maps (list of key-value pairs) with the > following keys > > # - srcblk = Source block to connect > > # - srcport = Port on the source block to connect > > # - dstblk = Destination block to connect > > # - dstport = Port on the destination block to connect > > connections: > > # TX A > > - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } > > # RX A > > - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } > > # TX B > > - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } > > # RX B > > - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } > > # > > # BSP Connections > > - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport > } > > - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } > > - { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time } > > # add replay block > > # ep4 to replay0(0) > > - { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 } > > # replay0(0) to ep4 > > - { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 } > > # ep5 to replay0(1) > > - { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 } > > # replay0(1) to ep5 > > - { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 } > > # BSP Connections > > - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram } > > # A list of all clock domain connections in design > > # ------------------------------------------------ > > # Format: A list of connection maps (list of key-value pairs) with the > following keys > > # - srcblk = Source block to connect (Always "_device"_) > > # - srcport = Clock domain on the source block to connect > > # - dstblk = Destination block to connect > > # - dstport = Clock domain on the destination block to connect > > clk_domains: > > - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } > > # add replay block > > - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } > > > Then I run the command: > > $ DRAM=1 rfnoc_image_builder -y e310_rfnoc_image_core.yml --fpga-dir > ~/workarea/uhd/fpga > > > After a while, the command throws me an error: > > > > I am using UHD 4.3 installed on Ubuntu 20.04. > > > Any suggestions? > > > Thanks, > > Yan > > > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
e310_replay_image_core.yml
Description: Binary data
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