I've been working on a software keying loop with the GPIO on an X310, and I measured the latency for setting a GPIO pin output wrapped back into a GPIO input to be around 5 ms on average. This was done by setting a pin manually, and then immediately polling the input pin to see how long before it switched states.
I haven't had anyone who could look at the FPGA side of the X310 yet, but I was wondering if it would be even possible to implement something in the FPGA like the ATR functionality, except it would allow for a keying loop (a Clear to Send GPIO output wrapping to a Request to Send GPIO input) and prevent transmission until the condition was true. I'm hoping that would significantly decrease the latency (less than 1 ms, hopefully) if I don't have to bother polling the pin. Right now I'm using: UHD 4.0, and GNU Radio 3.9.5. Thanks and regards, Jeff
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