Hi, In the framework of a research project, I need to be able to use the FPGA PS to modify the internal PPS (postpone or anticipate a single PPS pulse). I've modified the design to manipulate the internal counter of the n3xx_clocking/pps_gen_25 module. The latter generates the internal PPS in the clock domain @ref_clk. Before being sent to the RFNoC network (n3xx_core), and therefore to the timekeeper, the PPS passes into the DbCore block (A and B) to be sampled in @sample_clk domain. Inside DbCore the PPS is sent to the TdcTop block (CrossTrigger.vhd) which move the signal to @sample_clk domain using a complex mechanism based on two pulses (RpTrnsferPulse and SpTransferPulse). This mechanism prevents me to act freely on the PPS position (in the @sample_clk domain).
I have been trying to understand the purpose of this complicated method to switch between a clock domain to another, but I can't find a clear explanations. I noticed that the white rabbit PPS and the internal PPS use the same code (TdcWrapper.vhd) for the transition from ref_clk to sample_clk. I wonder if the CrossTrigger module is really needed to handle the internally generated PPS. Can anyone explain to me the reasoning behind this section of the n320 code? \ Ideally I would like to be able to go from ref_clk to sample_clk more directly and thus be able to directly reflect the changes I apply to pps_gen_25also to the PPS used by the timekeeper.
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