I’m trying to build the x310 base image on RHEL9. I keep getting build errors, despite the fact that I built UHD 4.2 no problem. The steps I followed:
1. Check out the v4.3.0.0 tag 2. source setupenv.sh --vivado-path=/path/to/Xilinx/Vivado/ 3. make X310_XG Did the process for building change? Has anybody else encountered problems? Here is the error message I’m getting plus some context: ======================================================== BUILDER: Building IP axi_hb31 ======================================================== BUILDER: Staging IP in build directory... BUILDER: Reserving IP location: /afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31 BUILDER: Retargeting IP to part kintex7/xc7k410t/ffg900/-2... BUILDER: Building IP... \[00:00:00\] Executing command: vivado -mode batch -source /afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log axi_hb31.log -nojournal WARNING: \[IP_Flow 19-2162\] IP 'axi_hb31' is locked: CRITICAL WARNING: \[filemgmt 20-1366\] Unable to reset target(s) for the following file is locked: /afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci CRITICAL WARNING: \[filemgmt 20-1365\] Unable to generate target(s) for the following file is locked: /afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci \[00:00:19\] Current task: Initialization +++ Current Phase: Starting \[00:00:19\] Current task: Initialization +++ Current Phase: Finished \[00:00:19\] Executing Tcl: synth_design -top axi_hb31 -part xc7k410tffg900-2 -mode out_of_context \[00:00:19\] Starting Synthesis Command WARNING: \[Vivado_Tcl 4-391\] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design. WARNING: \[IP_Flow 19-2162\] IP 'axi_hb31' is locked: ERROR: \[Designutils 20-414\] HRTInvokeSpec : No Verilog or VHDL sources specified ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml' CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml' CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml' CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml' CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml' \[00:00:20\] Current task: Synthesis +++ Current Phase: Starting ERROR: \[Vivado 12-398\] No designs are open \[00:00:20\] Current task: Synthesis +++ Current Phase: Finished \[00:00:20\] Process terminated. Status: Failure ======================================================== Warnings: 3 Critical Warnings: 7 Errors: 8 BUILDER: Releasing IP location: /afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31 make\[1\]: \*\*\* \[/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/lib/ip/axi_hb31/Makefile.inc:20: LIB_IP_AXI_HB31_TRGT\] Error 1 make\[1\]: Leaving directory '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300' make: \*\*\* \[Makefile:80: X310_IP\] Error 2
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