Here's a quick explanation. FPGAs have clocks that control the transfer of data between its internal registers. The Xilinx Vivado tool does a timing check during build to make sure that the paths from each driving register to each receiving register is not too long for the specified clock period. When it says "The design did not satisfy timing constraints" it means it couldn't arrange the logic on the chip to meet one or more of the clock requirements. There are several reasons this might happen:
- You added new logic to the design with too much logic between registers. In this case, you should modify your code to make meeting timing easier. - You added new logic, but made a mistake where it's trying to use the wrong clock or reset for something, which makes it impossible to meet timing. In this case you would need to correct your logic design. - The design has become too crowded, making it difficult for the tools to meet the timing requirements. In this case you might need to remove something to make more room. - Bad luck. The tools use some randomness to find solutions to really hard problems, and sometimes it just doesn't find a good solution even when one is possible. In this case you can just make a minor change to the design and build again to see if it does better the second time. If you don't change anything, it will typically give you identical results each time. The FPGA tools produce a timing report that says exactly which path failed to meet timing. Sometimes that can point you in the right direction. But sometimes the path that failed only failed because of another path that's even more difficult. Take a look at build-X310_HG/post_route_timing_summary.rpt and search for "(VIOLATED)" to find the path(s) that failed. Wade On Thu, Dec 22, 2022 at 7:18 PM Marcus D. Leech <[email protected]> wrote: > On 22/12/2022 20:11, AERMAN TUERXUN. wrote: > > Hi, > > > > I am building a custom RFNoC block on USRP X310. > > When I was trying to build bitstream, after almost two hours > > processing, it gave me the error as below. > > > > Do you have any idea what timing constraints are? > > Is that because the custom IP is too large for FPGA? > > Thank you! > I'm not an FPGA person, per se, but in general failure to meet timing > means that the layout engine cannot > find a layout in which all the signals that are supposed to arrived > "together" do so within the appropriate > timing windows. It is the case, in my previous experience with FPGA > designs, that the larger the design, > the harder it is for the layout engine to find a layout that > satisfies timing for all the timing-critical pieces > of the design. > > Others on this list have vastly more experience than me and can amplify > on this. The general question of > "what are timing constraints" is MUCH more of a general "designing > with FPGAs" question than a UHD > question or even an RFNoC question, per se. But there may be aspects > of the RFNoC universe that make > this a more frequent problem in adding custom bits and pieces to the > standard design. > > > > > > It started after > > [01:58:36] Executing Tcl: write_bitstream -force > > /home/xxxxx/uhd/fpga/usrp3/top/x300/build-X310_HG/x300.bit > > [01:58:36] Starting Write Bitstream Command > > ... (omit same CRITICAL WARNING) > > CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL > > u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a > > clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 > > > u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_dq.idelaye2 > > > has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL > > REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. > > CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL > > u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a > > clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 > > > u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2 > > > has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL > > REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. > > ERROR: [Builder 0-0] The design did not satisfy timing constraints. > > (Implementation outputs were still generated) > > ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors. > > [02:00:08] Current task: Write Bitstream +++ Current Phase: Starting > > [02:00:08] Current task: Write Bitstream +++ Current Phase: Finished > > [02:00:08] Process terminated. Status: Failure > > > > ======================================================== > > Warnings: 1121 > > Critical Warnings: 113 > > Errors: 2 > > > > make[5]: *** [Makefile.x300.inc:127: bin] Error 1 > > make[4]: *** [Makefile:85: X310_HG] Error 2 > > > > > > _______________________________________________ > > USRP-users mailing list -- [email protected] > > To unsubscribe send an email to [email protected] > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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