On 24/05/2023 16:22, m...@chaosinc.com wrote:
Thanks. Two follow up questions:
1.
For a given sample rate, is there a way to deterministically
calculate the group delay?
Look at the filter code in the version of the FPGA image that you're
using, determine which filter bits and
pieces are "in circuit" when you select your sample-rate, and
calculate the group delay from that.
Many folks who have run into the same problem have used a "measure it
in the lab" approach, and done
that for new releases of the FPGA code--the R&D team does
occasionally make changes to the filter
parameters and "doctrine" in order to optimize for certain types of
applications. This may well
de-optimize for others. SDRs are general-purpose devices, which
means that there will be cases where they
aren't "out of the factory" optimized for any *particular* application.
The approach some have take is to pad at one end or the other (or both)
to account for these delays, which comprise
a deterministic-but-version-dependent component, and an analog
component that is less deterministic, but at much
smaller times scales.
1.
Why do I not see the same delay at the back end of the
transmission (i.e. after the GPIO goes low)?
My suspicion is that part of what you're seeing is an analog switching
effect, and things like turn-on/turn-off
times are not perfectly symmetric.
This issue (lack of tight synchronization between ATR signals and actual
waveforms appearing at the antenna) has been
an issue in digital comms since I got involved in the 1980s, albeit,
in the 1980s, the time-scales were much larger.
You simply had to account for these effects for every new radio your
application encountered. In the DSP age, the
effects are at much smaller time-scales, but so are the data rates.
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