I don't see any bypass logic in the FPGA code, but in any case, the N320 only supports three master clock rates, none of which is our desired sampling rate: https://kb.ettus.com/USRP_N300/N310/N320/N321_Getting_Started_Guide#Supported_Sample_Rates
On Tue, May 30, 2023 at 11:44 AM Brian Padalino <bpadal...@gmail.com> wrote: > On Tue, May 30, 2023 at 2:27 PM Mena Ghebranious <m...@chaosinc.com> > wrote: > >> Yes, bypassing the DUC was discussed among our team, but as far as I can >> tell, there is no way to configure the bypass via the UHD/USRP API - it >> would require an FPGA mod. >> > > If you set the input rate to the radio to be the master clock rate (i.e. > the radio sample rate), then it should bypass it automatically with the > default FPGA image. > > Have you tried that? > > Brian > >>
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