On Tue, May 30, 2023 at 5:32 PM Mena Ghebranious <m...@chaosinc.com> wrote:
> I apologize, I think I must be missing something. This is the filter > (Xilinx IP) I see implemented in the N320 master code: > > > https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v#L3431 > This HBF seems to be external to the DUC, but I doubt it's killing a bunch of samples from coming out. > > > We are planning on running various sample rates running from 1 to possibly > 61.44Msps - for our current experiment we are using 20.480Msps > This is the most likely culprit. Currently you interpolate by 12 if you use a 245.76 Msps master clock rate using the DUC (HBF (x2) -> HBF (x2) -> CIC (x3) = 12). What you can do is interpolate to 245.76 Msps on the host for TX and you've got full control down to the sample. See what happens when you interpolate on the host instead of using the FPGA to do it for you. My guess is that it will be closer to what you want. Brian >
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