Hi Kevin,
there's no example, but there is a feature available that will let you do
that. You need to:
- Write a regular (System-)Verilog module that consumes any of the
available clocks, and produces your desired clock
- Internally, this module should instantiate an MMCM or whatever you use to
generate your clocks
- In rfnoc/modules/my_clk_module.yml you generate a YAML describing your
clock-generating module
- Make sure you declare your new clocks as output ("direction: out").
- In your image core YAML, declare the module like rfnoc blocks:
modules:
my_clock_foo:
block_desc: "my_foo.yml"
Now, your new clock is available for referencing in the clock domains
section.
--M
On Sat, Aug 2, 2025 at 1:53 PM Kevin Williams <kevin.willi...@vastech.co.za>
wrote:
> Hi,
>
>
>
> I have ip cores that provide an axi-lite interface for control registers,
> but which do not seem to make timing when that interface is connected to
> the rfnoc_ctrl clock in an x310 design.
>
>
>
> I read in the docs that from UHD 4.7 it is possible to define a new module
> to create this clock, but it isn’t clear how to implement this.
>
>
>
> Is there perhaps an example that someone could share?
>
>
>
> It would be first prize to generate a global clock that other of my rfnoc
> blocks could use but I don’t want to develop inside the UHD repo itself.
>
>
>
> Many thanks, Kevin
>
>
> _______________________________________________
> USRP-users mailing list -- usrp-users@lists.ettus.com
> To unsubscribe send an email to usrp-users-le...@lists.ettus.com
>
_______________________________________________
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-le...@lists.ettus.com
