Hi Eugene, I "think" that the replay block can act as a FIFO in recent UHD images. But, there is a possibility I am wrong such that there is a build-time parameter that is needed to config this. Another option would be DPDK if you are not already using it. Rob
On Mon, Jan 26, 2026 at 7:00 PM Eugene Grayver <[email protected]> wrote: > Hi, > > The default TX buffer for N32x is 128k samples = 512 kB. The box has 1 GB > of DRAM. I am getting occasional underflows when streaming at 200 Msps, > even though the CPU is not very loaded and easily meets the average > throughput. > > I have done all the usual stuff — isolated cores, pin threads to cores, > etc. > > Is there a way to increase the default DRAM buffer size w/out rebuilding > the FPGA image? > > Thanks. > > Eugene Grayver, Ph.D. > Principal Engineer > 310-336-1274 > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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