Thanks. I saw notes that seem to indicate that option. Anyone at Ettus/NI care to chime in as to how to do it? I found an example for E320 that shows an RFNoC .yml with a dram FIFO. I could make one for N320, but it is not clear how to use it from gnuradio. ________________________________ From: Rob Kossler <[email protected]> Sent: Tuesday, January 27, 2026 6:45 AM To: Eugene Grayver <[email protected]> Cc: usrp-users <[email protected]> Subject: [EXTERNAL] Re: [USRP-users] TX DRAM buffer
Do not open links or attachments unless you recognize the sender. If unsure, click the Report Phish button or forward the email to OPSEC. Hi Eugene, I "think" that the replay block can act as a FIFO in recent UHD images. But, there is a possibility I am wrong such that there is a build-time parameter that is needed to config this. Another option would be DPDK if you are not already using it. Rob On Mon, Jan 26, 2026 at 7:00 PM Eugene Grayver <[email protected]<mailto:[email protected]>> wrote: Hi, The default TX buffer for N32x is 128k samples = 512 kB. The box has 1 GB of DRAM. I am getting occasional underflows when streaming at 200 Msps, even though the CPU is not very loaded and easily meets the average throughput. I have done all the usual stuff — isolated cores, pin threads to cores, etc. Is there a way to increase the default DRAM buffer size w/out rebuilding the FPGA image? Thanks. Eugene Grayver, Ph.D. Principal Engineer 310-336-1274 _______________________________________________ USRP-users mailing list -- [email protected]<mailto:[email protected]> To unsubscribe send an email to [email protected]<mailto:[email protected]>
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