Reviewers: Benedikt Meurer,
Message:
ptal
Description:
[turbofan] support all shift operands on ia32
[email protected]
BUG=
Please review this at https://codereview.chromium.org/619663002/
SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge
Affected files (+26, -20 lines):
M src/compiler/ia32/code-generator-ia32.cc
M src/compiler/ia32/instruction-selector-ia32.cc
M src/ia32/assembler-ia32.h
M src/ia32/assembler-ia32.cc
M test/cctest/test-disasm-ia32.cc
Index: src/compiler/ia32/code-generator-ia32.cc
diff --git a/src/compiler/ia32/code-generator-ia32.cc
b/src/compiler/ia32/code-generator-ia32.cc
index
4bb75006640969a48f5fab52f9856e5290848b6e..84048b3e2a794c884b01c1f8c64589c1e0a654af
100644
--- a/src/compiler/ia32/code-generator-ia32.cc
+++ b/src/compiler/ia32/code-generator-ia32.cc
@@ -33,8 +33,6 @@ class IA32OperandConverter : public
InstructionOperandConverter {
Operand OutputOperand() { return ToOperand(instr_->Output()); }
- Operand TempOperand(int index) { return
ToOperand(instr_->TempAt(index)); }
-
Operand ToOperand(InstructionOperand* op, int extra = 0) {
if (op->IsRegister()) {
DCHECK(extra == 0);
@@ -280,30 +278,30 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
break;
case kIA32Shl:
if (HasImmediateInput(instr, 1)) {
- __ shl(i.OutputRegister(), i.InputInt5(1));
+ __ shl(i.OutputOperand(), i.InputInt5(1));
} else {
- __ shl_cl(i.OutputRegister());
+ __ shl_cl(i.OutputOperand());
}
break;
case kIA32Shr:
if (HasImmediateInput(instr, 1)) {
- __ shr(i.OutputRegister(), i.InputInt5(1));
+ __ shr(i.OutputOperand(), i.InputInt5(1));
} else {
- __ shr_cl(i.OutputRegister());
+ __ shr_cl(i.OutputOperand());
}
break;
case kIA32Sar:
if (HasImmediateInput(instr, 1)) {
- __ sar(i.OutputRegister(), i.InputInt5(1));
+ __ sar(i.OutputOperand(), i.InputInt5(1));
} else {
- __ sar_cl(i.OutputRegister());
+ __ sar_cl(i.OutputOperand());
}
break;
case kIA32Ror:
if (HasImmediateInput(instr, 1)) {
- __ ror(i.OutputRegister(), i.InputInt5(1));
+ __ ror(i.OutputOperand(), i.InputInt5(1));
} else {
- __ ror_cl(i.OutputRegister());
+ __ ror_cl(i.OutputOperand());
}
break;
case kSSEFloat64Cmp:
Index: src/compiler/ia32/instruction-selector-ia32.cc
diff --git a/src/compiler/ia32/instruction-selector-ia32.cc
b/src/compiler/ia32/instruction-selector-ia32.cc
index
b252e71e0395eaf099f360d6404ceac45c021bad..8d3e69ae1466204e87d3859610f792e842bd36da
100644
--- a/src/compiler/ia32/instruction-selector-ia32.cc
+++ b/src/compiler/ia32/instruction-selector-ia32.cc
@@ -329,9 +329,8 @@ static inline void VisitShift(InstructionSelector*
selector, Node* node,
Node* left = node->InputAt(0);
Node* right = node->InputAt(1);
- // TODO(turbofan): assembler only supports some addressing modes for
shifts.
if (g.CanBeImmediate(right)) {
- selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
+ selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
g.UseImmediate(right));
} else {
Int32BinopMatcher m(node);
@@ -341,7 +340,7 @@ static inline void VisitShift(InstructionSelector*
selector, Node* node,
right = mright.left().node();
}
}
- selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
+ selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
g.UseFixed(right, ecx));
}
}
Index: src/ia32/assembler-ia32.cc
diff --git a/src/ia32/assembler-ia32.cc b/src/ia32/assembler-ia32.cc
index
fd6a8d6f986961945a780b45a5549e15ac8676cf..5e8333d11a7ca9539ef343c5ae80524fb43b2c1b
100644
--- a/src/ia32/assembler-ia32.cc
+++ b/src/ia32/assembler-ia32.cc
@@ -982,24 +982,24 @@ void Assembler::rcr(Register dst, uint8_t imm8) {
}
-void Assembler::ror(Register dst, uint8_t imm8) {
+void Assembler::ror(const Operand& dst, uint8_t imm8) {
EnsureSpace ensure_space(this);
DCHECK(is_uint5(imm8)); // illegal shift count
if (imm8 == 1) {
EMIT(0xD1);
- EMIT(0xC8 | dst.code());
+ emit_operand(ecx, dst);
} else {
EMIT(0xC1);
- EMIT(0xC8 | dst.code());
+ emit_operand(ecx, dst);
EMIT(imm8);
}
}
-void Assembler::ror_cl(Register dst) {
+void Assembler::ror_cl(const Operand& dst) {
EnsureSpace ensure_space(this);
EMIT(0xD3);
- EMIT(0xC8 | dst.code());
+ emit_operand(ecx, dst);
}
Index: src/ia32/assembler-ia32.h
diff --git a/src/ia32/assembler-ia32.h b/src/ia32/assembler-ia32.h
index
cb1765521f1d8ac656ac5740367d366ffdb2947b..4532a67065cd8ff72be056b252714bdb2c5fead7
100644
--- a/src/ia32/assembler-ia32.h
+++ b/src/ia32/assembler-ia32.h
@@ -740,8 +740,11 @@ class Assembler : public AssemblerBase {
void rcl(Register dst, uint8_t imm8);
void rcr(Register dst, uint8_t imm8);
- void ror(Register dst, uint8_t imm8);
- void ror_cl(Register dst);
+
+ void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); }
+ void ror(const Operand& dst, uint8_t imm8);
+ void ror_cl(Register dst) { ror_cl(Operand(dst)); }
+ void ror_cl(const Operand& dst);
void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
void sar(const Operand& dst, uint8_t imm8);
Index: test/cctest/test-disasm-ia32.cc
diff --git a/test/cctest/test-disasm-ia32.cc
b/test/cctest/test-disasm-ia32.cc
index
49088f6e94da8223ad3afc124ac85d637e958350..8615d86086b964ff5368ec43fd2c0af7934457f9
100644
--- a/test/cctest/test-disasm-ia32.cc
+++ b/test/cctest/test-disasm-ia32.cc
@@ -201,6 +201,12 @@ TEST(DisasmIa320) {
__ rcl(edx, 7);
__ rcr(edx, 1);
__ rcr(edx, 7);
+ __ ror(edx, 1);
+ __ ror(edx, 6);
+ __ ror_cl(edx);
+ __ ror(Operand(ebx, ecx, times_4, 10000), 1);
+ __ ror(Operand(ebx, ecx, times_4, 10000), 6);
+ __ ror_cl(Operand(ebx, ecx, times_4, 10000));
__ sar(edx, 1);
__ sar(edx, 6);
__ sar_cl(edx);
--
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