Reviewers: Sven Panne,
Message:
Committed patchset #1 (id:1) manually as
3c79e2e920ccf49dc5841a0b4ce3323f11d24ec0 (presubmit successful).
Description:
[x64] Recognize MOVSXWL.
Also add some debug code to verify correct zero extension of 32-bit
moves.
TEST=mjsunit/asm
[email protected]
Committed:
https://chromium.googlesource.com/v8/v8/+/3c79e2e920ccf49dc5841a0b4ce3323f11d24ec0
Please review this at https://codereview.chromium.org/736623002/
Base URL: https://chromium.googlesource.com/v8/v8.git@master
Affected files (+33, -1 lines):
M src/compiler/x64/code-generator-x64.cc
M src/compiler/x64/instruction-selector-x64.cc
M src/x64/assembler-x64.h
M src/x64/assembler-x64.cc
Index: src/compiler/x64/code-generator-x64.cc
diff --git a/src/compiler/x64/code-generator-x64.cc
b/src/compiler/x64/code-generator-x64.cc
index
a867f4a72c880e0211859ec7e8ac2996d64dc8d0..8a61d371bffed90e013b224aa674927407e9b63a
100644
--- a/src/compiler/x64/code-generator-x64.cc
+++ b/src/compiler/x64/code-generator-x64.cc
@@ -484,6 +484,7 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
break;
case kX64Movsxbl:
__ movsxbl(i.OutputRegister(), i.MemoryOperand());
+ __ AssertZeroExtended(i.OutputRegister());
break;
case kX64Movzxbl:
__ movzxbl(i.OutputRegister(), i.MemoryOperand());
@@ -499,10 +500,18 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
break;
}
case kX64Movsxwl:
- __ movsxwl(i.OutputRegister(), i.MemoryOperand());
+ if (instr->addressing_mode() != kMode_None) {
+ __ movsxwl(i.OutputRegister(), i.MemoryOperand());
+ } else if (instr->InputAt(0)->IsRegister()) {
+ __ movsxwl(i.OutputRegister(), i.InputRegister(0));
+ } else {
+ __ movsxwl(i.OutputRegister(), i.InputOperand(0));
+ }
+ __ AssertZeroExtended(i.OutputRegister());
break;
case kX64Movzxwl:
__ movzxwl(i.OutputRegister(), i.MemoryOperand());
+ __ AssertZeroExtended(i.OutputRegister());
break;
case kX64Movw: {
int index = 0;
@@ -525,6 +534,7 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
} else {
__ movl(i.OutputRegister(), i.MemoryOperand());
}
+ __ AssertZeroExtended(i.OutputRegister());
} else {
int index = 0;
Operand operand = i.MemoryOperand(&index);
@@ -576,6 +586,7 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
break;
case kX64Lea32:
__ leal(i.OutputRegister(), i.MemoryOperand());
+ __ AssertZeroExtended(i.OutputRegister());
break;
case kX64Lea:
__ leaq(i.OutputRegister(), i.MemoryOperand());
Index: src/compiler/x64/instruction-selector-x64.cc
diff --git a/src/compiler/x64/instruction-selector-x64.cc
b/src/compiler/x64/instruction-selector-x64.cc
index
fe668587099e1394f6cb8d99a2d4ebcf7400d9b5..d89daf25306a89882a8c1c8a961f7509ceea3b10
100644
--- a/src/compiler/x64/instruction-selector-x64.cc
+++ b/src/compiler/x64/instruction-selector-x64.cc
@@ -346,6 +346,15 @@ void InstructionSelector::VisitWord64Shr(Node* node) {
void InstructionSelector::VisitWord32Sar(Node* node) {
+ X64OperandGenerator g(this);
+ Int32BinopMatcher m(node);
+ if (CanCover(m.node(), m.left().node()) && m.left().IsWord32Shl()) {
+ Int32BinopMatcher mleft(m.left().node());
+ if (mleft.right().Is(16) && m.right().Is(16)) {
+ Emit(kX64Movsxwl, g.DefineAsRegister(node),
g.Use(mleft.left().node()));
+ return;
+ }
+ }
VisitWord32Shift(this, node, kX64Sar32);
}
@@ -364,6 +373,7 @@ void InstructionSelector::VisitWord64Ror(Node* node) {
VisitWord64Shift(this, node, kX64Ror);
}
+
namespace {
AddressingMode GenerateMemoryOperandInputs(X64OperandGenerator* g, Node*
scaled,
@@ -1161,6 +1171,7 @@ InstructionSelector::SupportedMachineOperatorFlags() {
}
return MachineOperatorBuilder::kNoFlags;
}
+
} // namespace compiler
} // namespace internal
} // namespace v8
Index: src/x64/assembler-x64.cc
diff --git a/src/x64/assembler-x64.cc b/src/x64/assembler-x64.cc
index
dfd51a4bedfc4990778778e3b36bbc2bebb77e14..0bcdf24d6f0f236900ca9be05b9ddacfba2e082d
100644
--- a/src/x64/assembler-x64.cc
+++ b/src/x64/assembler-x64.cc
@@ -1401,6 +1401,15 @@ void Assembler::movsxbq(Register dst, const Operand&
src) {
}
+void Assembler::movsxwl(Register dst, Register src) {
+ EnsureSpace ensure_space(this);
+ emit_optional_rex_32(dst, src);
+ emit(0x0F);
+ emit(0xBF);
+ emit_modrm(dst, src);
+}
+
+
void Assembler::movsxwl(Register dst, const Operand& src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
Index: src/x64/assembler-x64.h
diff --git a/src/x64/assembler-x64.h b/src/x64/assembler-x64.h
index
3b55396c14877163b50e63cc86a1a70681ca476a..8a070a656cd02304a7fc3ccdc38669ca8168ffcd
100644
--- a/src/x64/assembler-x64.h
+++ b/src/x64/assembler-x64.h
@@ -733,6 +733,7 @@ class Assembler : public AssemblerBase {
void movsxbl(Register dst, const Operand& src);
void movsxbq(Register dst, const Operand& src);
+ void movsxwl(Register dst, Register src);
void movsxwl(Register dst, const Operand& src);
void movsxwq(Register dst, const Operand& src);
void movsxlq(Register dst, Register src);
--
--
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