Reviewers: JF, rmcilroy,
Message:
On 2014/12/15 04:59:39, arajp wrote:
mailto:[email protected] changed reviewers:
+ mailto:[email protected], mailto:[email protected]
JFB,
This is the same patch I took over from Srikumar since he is on a long
vacation.
PTAL.
Description:
Make FlushICache NOP for Nvidia Denver CPU's.
BUG=
Please review this at https://codereview.chromium.org/797233002/
Base URL: https://chromium.googlesource.com/v8/v8.git@master
Affected files (+41, -2 lines):
M src/arm/assembler-arm.cc
M src/arm/cpu-arm.cc
M src/arm64/assembler-arm64.cc
M src/arm64/cpu-arm64.cc
M src/base/cpu.h
M src/base/cpu.cc
M src/globals.h
Index: src/arm/assembler-arm.cc
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index
8fadb7606c8f0c8203d443ab9e1eb0622eb527b6..6d90179e7bf2e4b61f270753547edd15a4387031
100644
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -127,6 +127,10 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
}
if (FLAG_enable_32dregs && cpu.has_vfp3_d32()) supported_ |= 1u <<
VFP32DREGS;
+
+ if (cpu.implementer() == base::CPU::NVIDIA &&
+ cpu.variant() == base::CPU::NV_VARIANT_DENVER)
+ supported_ |= 1u << COHERENT_CACHE;
#endif
DCHECK(!IsSupported(VFP3) || IsSupported(ARMv7));
@@ -188,14 +192,15 @@ void CpuFeatures::PrintTarget() {
void CpuFeatures::PrintFeatures() {
printf(
"ARMv7=%d VFP3=%d VFP32DREGS=%d NEON=%d SUDIV=%d
UNALIGNED_ACCESSES=%d "
- "MOVW_MOVT_IMMEDIATE_LOADS=%d",
+ "MOVW_MOVT_IMMEDIATE_LOADS=%d COHERENT_CACHE=%d",
CpuFeatures::IsSupported(ARMv7),
CpuFeatures::IsSupported(VFP3),
CpuFeatures::IsSupported(VFP32DREGS),
CpuFeatures::IsSupported(NEON),
CpuFeatures::IsSupported(SUDIV),
CpuFeatures::IsSupported(UNALIGNED_ACCESSES),
- CpuFeatures::IsSupported(MOVW_MOVT_IMMEDIATE_LOADS));
+ CpuFeatures::IsSupported(MOVW_MOVT_IMMEDIATE_LOADS),
+ CpuFeatures::IsSupported(COHERENT_CACHE));
#ifdef __arm__
bool eabi_hardfloat = base::OS::ArmUsingHardFloat();
#elif USE_EABI_HARDFLOAT
Index: src/arm/cpu-arm.cc
diff --git a/src/arm/cpu-arm.cc b/src/arm/cpu-arm.cc
index
9c7104eb95a72961d3abffbb8cf0054a30eb183c..4a340708f9334faa7a59d127e9518067beca85e4
100644
--- a/src/arm/cpu-arm.cc
+++ b/src/arm/cpu-arm.cc
@@ -27,6 +27,8 @@ namespace internal {
void CpuFeatures::FlushICache(void* start, size_t size) {
if (size == 0) return;
+ if (CpuFeatures::IsSupported(COHERENT_CACHE)) return;
+
#if defined(USE_SIMULATOR)
// Not generating ARM instructions for C-code. This means that we are
// building an ARM emulator based target. We should notify the simulator
Index: src/arm64/assembler-arm64.cc
diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
index
524be154c53bef81a410c3c648f456fc32f85bd3..97970a1cba20b6af5c3d717f0ebec9e07b34061e
100644
--- a/src/arm64/assembler-arm64.cc
+++ b/src/arm64/assembler-arm64.cc
@@ -46,6 +46,11 @@ namespace internal {
void CpuFeatures::ProbeImpl(bool cross_compile) {
// AArch64 has no configuration options, no further probing is required.
supported_ = 0;
+ // Probe for runtime features
+ base::CPU cpu;
+ if (cpu.implementer() == base::CPU::NVIDIA &&
+ cpu.variant() == base::CPU::NV_VARIANT_DENVER)
+ supported_ |= 1u << COHERENT_CACHE;
}
Index: src/arm64/cpu-arm64.cc
diff --git a/src/arm64/cpu-arm64.cc b/src/arm64/cpu-arm64.cc
index
39beb6d9ef86342a4bf470a5ec329023b1795a5e..11ba7c98a0d20764f3a775e4fc66dfa083b13e13
100644
--- a/src/arm64/cpu-arm64.cc
+++ b/src/arm64/cpu-arm64.cc
@@ -43,6 +43,8 @@ class CacheLineSizes {
void CpuFeatures::FlushICache(void* address, size_t length) {
if (length == 0) return;
+ if (CpuFeatures::IsSupported(COHERENT_CACHE)) return;
+
#ifdef USE_SIMULATOR
// TODO(all): consider doing some cache simulation to ensure every
address
// run has been synced.
Index: src/base/cpu.cc
diff --git a/src/base/cpu.cc b/src/base/cpu.cc
index
e188406f1a21ff72226b17c2332eb7ccd942dd49..0fcb2c08350964f63a5e87b34ed25b791dc02292
100644
--- a/src/base/cpu.cc
+++ b/src/base/cpu.cc
@@ -300,6 +300,7 @@ CPU::CPU()
type_(0),
implementer_(0),
architecture_(0),
+ variant_(-1),
part_(0),
has_fpu_(false),
has_cmov_(false),
@@ -396,6 +397,16 @@ CPU::CPU()
delete[] implementer;
}
+ char* variant = cpu_info.ExtractField("CPU variant");
+ if (variant != NULL) {
+ char* end ;
+ variant_ = strtol(variant, &end, 0);
+ if (end == variant) {
+ variant_ = 0;
+ }
+ delete[] variant;
+ }
+
// Extract part number from the "CPU part" field.
char* part = cpu_info.ExtractField("CPU part");
if (part != NULL) {
@@ -548,6 +559,16 @@ CPU::CPU()
delete[] implementer;
}
+ char* variant = cpu_info.ExtractField("CPU variant");
+ if (variant != NULL) {
+ char* end ;
+ variant_ = strtol(variant, &end, 0);
+ if (end == variant) {
+ variant_ = 0;
+ }
+ delete[] variant;
+ }
+
// Extract part number from the "CPU part" field.
char* part = cpu_info.ExtractField("CPU part");
if (part != NULL) {
Index: src/base/cpu.h
diff --git a/src/base/cpu.h b/src/base/cpu.h
index
fe8e1029757f0d37806247366b307eb3e3c13ad7..95b4e2023b57a2af8d12fb69490d6a203cb99be0
100644
--- a/src/base/cpu.h
+++ b/src/base/cpu.h
@@ -47,6 +47,8 @@ class CPU FINAL {
static const int NVIDIA = 0x4e;
static const int QUALCOMM = 0x51;
int architecture() const { return architecture_; }
+ int variant() const { return variant_; }
+ static const int NV_VARIANT_DENVER = 0x0;
int part() const { return part_; }
static const int ARM_CORTEX_A5 = 0xc05;
static const int ARM_CORTEX_A7 = 0xc07;
@@ -92,6 +94,7 @@ class CPU FINAL {
int type_;
int implementer_;
int architecture_;
+ int variant_;
int part_;
bool has_fpu_;
bool has_cmov_;
Index: src/globals.h
diff --git a/src/globals.h b/src/globals.h
index
3a83f2cbee1d9a091d8c4cb6895ed0ab44c45485..933c6e25e33ed0a835f4bf362971c23c84b055e4
100644
--- a/src/globals.h
+++ b/src/globals.h
@@ -623,6 +623,7 @@ enum CpuFeature {
MIPSr6,
// ARM64
ALWAYS_ALIGN_CSP,
+ COHERENT_CACHE,
NUMBER_OF_CPU_FEATURES
};
--
--
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