Reviewers: William Hesse, Message: This is a small optimization for x64.
It saves 1 byte in encoding xor reg, reg (i.e. when using xor to zero a register). Description: Generate more compact XOR on 64-bit architecture when using xor to zero out registers. When using xor to zero a 64-bit register, generate 32-bit instruction instead. (according to Intel 64-bit mode coding guidelines) previous code for zeroing RAX: xor rax, rax ==> new code for zeroing RAX: xor eax, eax The 32-bit operand form has the same semantics: It also zeroes the upper 32-bit of rax and its encoding uses 1 byte less. Please review this at http://codereview.chromium.org/330018 SVN Base: http://v8.googlecode.com/svn/branches/bleeding_edge/ Affected files: M src/x64/assembler-x64.h Index: src/x64/assembler-x64.h =================================================================== --- src/x64/assembler-x64.h (revision 3123) +++ src/x64/assembler-x64.h (working copy) @@ -920,7 +920,11 @@ void testq(Register dst, Immediate mask); void xor_(Register dst, Register src) { - arithmetic_op(0x33, dst, src); + if (dst.code() == src.code()) { + arithmetic_op_32(0x33, dst, src); + } else { + arithmetic_op(0x33, dst, src); + } } void xorl(Register dst, Register src) { --~--~---------~--~----~------------~-------~--~----~ v8-dev mailing list [email protected] http://groups.google.com/group/v8-dev -~----------~----~----~----~------~----~------~--~---
