Reviewers: danno, Benedikt Meurer, paul.l..., dusmil.imgtec,
akos.palfi.imgtec, gergely.kis.imgtec,
Description:
MIPS: [turbofan] Unify Math.floor / Math.ceil optimization.
Port 022ea7e05779f07b9327bcc2d4709fc80b2aeecb
Original commit message:
Provide an intrinsic %MathFloor / %_MathFloor that is used to optimize
both Math.ceil and Math.floor, and use the JS inlining mechanism to
inline Math.ceil into TurboFan code. Although we need to touch code
outside of TurboFan to make this work, this does not affect the way we
handle Math.ceil and/or Math.floor in CrankShaft, because for CrankShaft
the old-style builtin function id based inlining still kicks in first.
Once this solution is stabilized, we can use it for Math.floor as well.
And once that is settled, we can establish it as the unified way to
inline builtins, and get rid of the specialized builtin function id
based inlining at some point.
Note that "builtin" applies to basically every piece of internal
JavaScript/intrinsics based code, so this also applies to the yet to be
defined JavaScript based code stubs and handlers.
BUG=v8:3953
LOG=n
Please review this at https://codereview.chromium.org/998503002/
Base URL: https://chromium.googlesource.com/v8/v8.git@master
Affected files (+48, -32 lines):
M src/compiler/mips/code-generator-mips.cc
M src/compiler/mips/instruction-codes-mips.h
M src/compiler/mips/instruction-selector-mips.cc
M src/compiler/mips64/code-generator-mips64.cc
M src/compiler/mips64/instruction-codes-mips64.h
M src/compiler/mips64/instruction-selector-mips64.cc
Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc
b/src/compiler/mips/code-generator-mips.cc
index
6c299b0f227e515707061a3dc226a9dd19275f0d..b354b3d8c048f2856cd453f773c6693b2ecf7484
100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -573,18 +573,18 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ MovFromFloatResult(i.OutputDoubleRegister());
break;
}
- case kMipsFloat64Floor: {
+ case kMipsFloat64RoundDown: {
ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(floor_l_d, Floor);
break;
}
- case kMipsFloat64Ceil: {
- ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(ceil_l_d, Ceil);
- break;
- }
case kMipsFloat64RoundTruncate: {
ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(trunc_l_d, Truncate);
break;
}
+ case kMipsFloat64RoundUp: {
+ ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(ceil_l_d, Ceil);
+ break;
+ }
case kMipsSqrtD: {
__ sqrt_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
break;
Index: src/compiler/mips/instruction-codes-mips.h
diff --git a/src/compiler/mips/instruction-codes-mips.h
b/src/compiler/mips/instruction-codes-mips.h
index
86817402f43767dee467bccb808be2241b0d87c5..e7f680dd2e779863b2fb844ca67424eea12835b8
100644
--- a/src/compiler/mips/instruction-codes-mips.h
+++ b/src/compiler/mips/instruction-codes-mips.h
@@ -40,9 +40,9 @@ namespace compiler {
V(MipsDivD) \
V(MipsModD) \
V(MipsSqrtD) \
- V(MipsFloat64Floor) \
- V(MipsFloat64Ceil) \
+ V(MipsFloat64RoundDown) \
V(MipsFloat64RoundTruncate) \
+ V(MipsFloat64RoundUp) \
V(MipsCvtSD) \
V(MipsCvtDS) \
V(MipsTruncWD) \
Index: src/compiler/mips/instruction-selector-mips.cc
diff --git a/src/compiler/mips/instruction-selector-mips.cc
b/src/compiler/mips/instruction-selector-mips.cc
index
32214b1be7c32037403f09a46ffb411639e6f4c0..427cc2c3b5c4d76da41600621c81d74c546ec7e9
100644
--- a/src/compiler/mips/instruction-selector-mips.cc
+++ b/src/compiler/mips/instruction-selector-mips.cc
@@ -402,6 +402,20 @@ void InstructionSelector::VisitFloat64Add(Node* node) {
void InstructionSelector::VisitFloat64Sub(Node* node) {
+ MipsOperandGenerator g(this);
+ Float64BinopMatcher m(node);
+ if (m.left().IsMinusZero() && m.right().IsFloat64RoundDown() &&
+ CanCover(m.node(), m.right().node())) {
+ if (m.right().InputAt(0)->opcode() == IrOpcode::kFloat64Sub &&
+ CanCover(m.right().node(), m.right().InputAt(0))) {
+ Float64BinopMatcher mright0(m.right().InputAt(0));
+ if (mright0.left().IsMinusZero()) {
+ Emit(kMipsFloat64RoundUp, g.DefineAsRegister(node),
+ g.UseRegister(mright0.right().node()));
+ return;
+ }
+ }
+ }
VisitRRR(this, kMipsSubD, node);
}
@@ -429,13 +443,8 @@ void InstructionSelector::VisitFloat64Sqrt(Node* node)
{
}
-void InstructionSelector::VisitFloat64Floor(Node* node) {
- VisitRR(this, kMipsFloat64Floor, node);
-}
-
-
-void InstructionSelector::VisitFloat64Ceil(Node* node) {
- VisitRR(this, kMipsFloat64Ceil, node);
+void InstructionSelector::VisitFloat64RoundDown(Node* node) {
+ VisitRR(this, kMipsFloat64RoundDown, node);
}
@@ -921,8 +930,7 @@ void
InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() {
if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
- return MachineOperatorBuilder::kFloat64Floor |
- MachineOperatorBuilder::kFloat64Ceil |
+ return MachineOperatorBuilder::kFloat64RoundDown |
MachineOperatorBuilder::kFloat64RoundTruncate;
}
return MachineOperatorBuilder::kNoFlags;
Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc
b/src/compiler/mips64/code-generator-mips64.cc
index
e6155aa149995dbf4ced457929184ec0c09f2ecb..e345352747c9c3b06385aee0549309a8a1bb0d68
100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -637,18 +637,18 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ MovFromFloatResult(i.OutputDoubleRegister());
break;
}
- case kMips64Float64Floor: {
+ case kMips64Float64RoundDown: {
ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(floor_l_d, Floor);
break;
}
- case kMips64Float64Ceil: {
- ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(ceil_l_d, Ceil);
- break;
- }
case kMips64Float64RoundTruncate: {
ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(trunc_l_d, Truncate);
break;
}
+ case kMips64Float64RoundUp: {
+ ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(ceil_l_d, Ceil);
+ break;
+ }
case kMips64SqrtD: {
__ sqrt_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
break;
Index: src/compiler/mips64/instruction-codes-mips64.h
diff --git a/src/compiler/mips64/instruction-codes-mips64.h
b/src/compiler/mips64/instruction-codes-mips64.h
index
bae6e24081195d29e2ab8d5b0f8da481038cf5bc..edd3ca4301f64c44cce46a3665f6bf47b18f0955
100644
--- a/src/compiler/mips64/instruction-codes-mips64.h
+++ b/src/compiler/mips64/instruction-codes-mips64.h
@@ -53,9 +53,9 @@ namespace compiler {
V(Mips64DivD) \
V(Mips64ModD) \
V(Mips64SqrtD) \
- V(Mips64Float64Floor) \
- V(Mips64Float64Ceil) \
+ V(Mips64Float64RoundDown) \
V(Mips64Float64RoundTruncate) \
+ V(Mips64Float64RoundUp) \
V(Mips64CvtSD) \
V(Mips64CvtDS) \
V(Mips64TruncWD) \
Index: src/compiler/mips64/instruction-selector-mips64.cc
diff --git a/src/compiler/mips64/instruction-selector-mips64.cc
b/src/compiler/mips64/instruction-selector-mips64.cc
index
6a8d7420e0c982d9ba90f6f3d76e425479d5a1a8..e75283093801ee169a3cb0e07000cb24761e4792
100644
--- a/src/compiler/mips64/instruction-selector-mips64.cc
+++ b/src/compiler/mips64/instruction-selector-mips64.cc
@@ -581,6 +581,20 @@ void InstructionSelector::VisitFloat64Add(Node* node) {
void InstructionSelector::VisitFloat64Sub(Node* node) {
+ Mips64OperandGenerator g(this);
+ Float64BinopMatcher m(node);
+ if (m.left().IsMinusZero() && m.right().IsFloat64RoundDown() &&
+ CanCover(m.node(), m.right().node())) {
+ if (m.right().InputAt(0)->opcode() == IrOpcode::kFloat64Sub &&
+ CanCover(m.right().node(), m.right().InputAt(0))) {
+ Float64BinopMatcher mright0(m.right().InputAt(0));
+ if (mright0.left().IsMinusZero()) {
+ Emit(kMips64Float64RoundUp, g.DefineAsRegister(node),
+ g.UseRegister(mright0.right().node()));
+ return;
+ }
+ }
+ }
VisitRRR(this, kMips64SubD, node);
}
@@ -609,13 +623,8 @@ void InstructionSelector::VisitFloat64Sqrt(Node* node)
{
}
-void InstructionSelector::VisitFloat64Floor(Node* node) {
- VisitRR(this, kMips64Float64Floor, node);
-}
-
-
-void InstructionSelector::VisitFloat64Ceil(Node* node) {
- VisitRR(this, kMips64Float64Ceil, node);
+void InstructionSelector::VisitFloat64RoundDown(Node* node) {
+ VisitRR(this, kMips64Float64RoundDown, node);
}
@@ -1172,8 +1181,7 @@ void
InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
// static
MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() {
- return MachineOperatorBuilder::kFloat64Floor |
- MachineOperatorBuilder::kFloat64Ceil |
+ return MachineOperatorBuilder::kFloat64RoundDown |
MachineOperatorBuilder::kFloat64RoundTruncate;
}
--
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