Reviewers: rmcilroy, Benedikt Meurer, arajp, Rodolph Perfetta (ARM),
avanbrunt,
Message:
I have added alex from nvidia cpu team to comment on variant() and part()
details for denver family.
Description:
Make FlushICache NOP for Nvidia Denver 1.0 only
FlushICache should be NOP for Denver with part numbers 0x0, 0x1 and 0x2
only.
Instruction cache needs to flushed for future versions of denver.
Please review this at https://codereview.chromium.org/1287173004/
Base URL: https://chromium.googlesource.com/v8/v8.git@lkgr
Affected files (+7, -2 lines):
M src/arm/assembler-arm.cc
M src/arm64/assembler-arm64.cc
M src/base/cpu.h
Index: src/arm/assembler-arm.cc
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index
862748c3f5da2ecf372af74492b5c6bf5ddccb3a..633b5d12c076b46e04343c9f2612928b21e46fd8
100644
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -126,7 +126,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
if (FLAG_enable_32dregs && cpu.has_vfp3_d32()) supported_ |= 1u <<
VFP32DREGS;
if (cpu.implementer() == base::CPU::NVIDIA &&
- cpu.variant() == base::CPU::NVIDIA_DENVER) {
+ cpu.variant() == base::CPU::NVIDIA_DENVER &&
+ cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
supported_ |= 1u << COHERENT_CACHE;
}
#endif
Index: src/arm64/assembler-arm64.cc
diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
index
8db7126fcf44c3be8c93d4453e3cece753a1eca8..235b5ee2bcaa96078ceddbb4f543133a4b040781
100644
--- a/src/arm64/assembler-arm64.cc
+++ b/src/arm64/assembler-arm64.cc
@@ -52,7 +52,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
// Probe for runtime features
base::CPU cpu;
if (cpu.implementer() == base::CPU::NVIDIA &&
- cpu.variant() == base::CPU::NVIDIA_DENVER) {
+ cpu.variant() == base::CPU::NVIDIA_DENVER &&
+ cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
supported_ |= 1u << COHERENT_CACHE;
}
}
Index: src/base/cpu.h
diff --git a/src/base/cpu.h b/src/base/cpu.h
index
f6c5a8506a00582d4fe81b230f0598dd5132c6ab..1dc0a91f6501129ca069fe0048bcc6c53dfcb330
100644
--- a/src/base/cpu.h
+++ b/src/base/cpu.h
@@ -59,6 +59,9 @@ class CPU final {
static const int ARM_CORTEX_A12 = 0xc0c;
static const int ARM_CORTEX_A15 = 0xc0f;
+ // Denver-specific part code
+ static const int NVIDIA_DENVER_V10 = 0x002;
+
// PPC-specific part codes
enum {
PPC_POWER5,
--
--
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