On 2015/08/19 16:35:39, avanbrunt wrote:
https://codereview.chromium.org/1287173004/diff/1/src/arm64/assembler-arm64.cc
File src/arm64/assembler-arm64.cc (right):
https://codereview.chromium.org/1287173004/diff/1/src/arm64/assembler-arm64.cc#newcode55
src/arm64/assembler-arm64.cc:55: cpu.variant() ==
base::CPU::NVIDIA_DENVER &&
On 2015/08/19 08:19:27, Rodolph Perfetta (ARM) wrote:
> Denver is a CPU part (like A57, A53 for ARM), so it looks like the
checks
are
> switched: part should be Denver and variant should be less than 0, 1 or
2.
no?
> The initial code was wrong then.
Implementer == 'N' and and variant == 0x0 combined identify the Denver
family.
The different implementations are distinguished by the primary part
number.
Part
number 0x000, 0x001, and 0x002 all have a coherent instruction cache.
I see. It is different on ARM (implementer and part define a CPU) so by
force of
habit I assumed the code was wrong. Sorry for that.
https://codereview.chromium.org/1287173004/
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