Reviewers: Erik Corry, Mads Ager,
Description:
Changed inlined property load detection on ARM
Instaed of having a nop after all non-inlined calls to load IC use a
different
nop (mov r1, r1 instead of mov r0, r0) to detect an inlined load IC.
Added more infrastructure to the deferred code handling to make it possbile
to
block constant pool emitting in a deferred code block, including the branch
instruction ending the deferred code block.
Addressed a couple of comments to http://codereview.chromium.org/1715003,
including adding an assert to make sure that the patching of an ldr
instruction
is always possible.
Please review this at http://codereview.chromium.org/1758003/show
SVN Base: http://v8.googlecode.com/svn/branches/bleeding_edge/
Affected files:
M src/arm/assembler-arm.h
M src/arm/assembler-arm.cc
M src/arm/codegen-arm.h
M src/arm/codegen-arm.cc
M src/arm/full-codegen-arm.cc
M src/arm/ic-arm.cc
M src/arm/virtual-frame-arm.h
M src/arm/virtual-frame-arm.cc
M src/codegen.h
M src/codegen.cc
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