Reviewers: Yang,
Description:
MIPS: port ARM: Fix context save/restore for VFP registers.
This commit was missed/skipped earlier for some reason.
Ported r8357 (d78dae4)
BUG=
TEST=
Please review this at http://codereview.chromium.org/7809014/
Affected files:
M src/mips/code-stubs-mips.cc
M src/mips/frames-mips.h
M src/mips/macro-assembler-mips.h
M src/mips/macro-assembler-mips.cc
Index: src/mips/code-stubs-mips.cc
diff --git a/src/mips/code-stubs-mips.cc b/src/mips/code-stubs-mips.cc
index
9385f2fda7af2fe9c6c03e393b91bddfd00deaa5..cad4bc78a90edad8f259f15398882147f4a104cf
100644
--- a/src/mips/code-stubs-mips.cc
+++ b/src/mips/code-stubs-mips.cc
@@ -3695,9 +3695,20 @@ void JSEntryStub::GenerateBody(MacroAssembler* masm,
bool is_construct) {
// Save callee saved registers on the stack.
__ MultiPush(kCalleeSaved | ra.bit());
+ if (CpuFeatures::IsSupported(FPU)) {
+ CpuFeatures::Scope scope(FPU);
+ // Save callee-saved FPU registers.
+ __ MultiPushFPU(kCalleeSavedFPU);
+ }
+
// Load argv in s0 register.
- __ lw(s0, MemOperand(sp, (kNumCalleeSaved + 1) * kPointerSize +
- StandardFrameConstants::kCArgsSlotsSize));
+ int offset_to_argv = (kNumCalleeSaved + 1) * kPointerSize;
+ if (CpuFeatures::IsSupported(FPU)) {
+ offset_to_argv += kNumCalleeSavedFPU * kDoubleSize;
+ }
+
+ __ lw(s0, MemOperand(sp, offset_to_argv +
+ StandardFrameConstants::kCArgsSlotsSize));
// We build an EntryFrame.
__ li(t3, Operand(-1)); // Push a bad frame pointer to fail if it is
used.
@@ -3829,6 +3840,8 @@ void JSEntryStub::GenerateBody(MacroAssembler* masm,
bool is_construct) {
// Reset the stack to the callee saved registers.
__ addiu(sp, sp, -EntryFrameConstants::kCallerFPOffset);
+ __ MultiPopFPU(kCalleeSavedFPU);
+
// Restore callee saved registers from the stack.
__ MultiPop(kCalleeSaved | ra.bit());
// Return.
Index: src/mips/frames-mips.h
diff --git a/src/mips/frames-mips.h b/src/mips/frames-mips.h
index
1899843a198d22484365dc2357bde396c918d5d4..0efde2d5f59c0ddb6f8385e06e2fc115a5b61606
100644
--- a/src/mips/frames-mips.h
+++ b/src/mips/frames-mips.h
@@ -30,7 +30,6 @@
#ifndef V8_MIPS_FRAMES_MIPS_H_
#define V8_MIPS_FRAMES_MIPS_H_
-
namespace v8 {
namespace internal {
@@ -64,6 +63,10 @@ static const RegList kCalleeSaved =
static const int kNumCalleeSaved = 9;
+static const RegList kCalleeSavedFPU =
+ 1 << 20 | 1 << 22 | 1 << 24 | 1 << 26 | 1 << 28 | 1 << 30;
+
+static const int kNumCalleeSavedFPU = 6;
// Number of registers for which space is reserved in safepoints. Must be a
// multiple of 8.
Index: src/mips/macro-assembler-mips.cc
diff --git a/src/mips/macro-assembler-mips.cc
b/src/mips/macro-assembler-mips.cc
index
c7f727bef604e1e0eff71ff0987b00b57f5d2c56..606b41db28fd42850fa9cb7cc3d371b4a490b0e1
100644
--- a/src/mips/macro-assembler-mips.cc
+++ b/src/mips/macro-assembler-mips.cc
@@ -752,6 +752,64 @@ void MacroAssembler::MultiPopReversed(RegList regs) {
}
+void MacroAssembler::MultiPushFPU(RegList regs) {
+ CpuFeatures::Scope scope(FPU);
+ int16_t NumSaved = 0;
+ int16_t NumToPush = NumberOfBitsSet(regs);
+
+ addiu(sp, sp, -8 * NumToPush);
+ for (int16_t i = kNumRegisters; i > 0; i--) {
+ if ((regs & (1 << i)) != 0) {
+ sdc1(FPURegister::from_code(i),
+ MemOperand(sp, 8 * (NumToPush - ++NumSaved)));
+ }
+ }
+}
+
+
+void MacroAssembler::MultiPushReversedFPU(RegList regs) {
+ CpuFeatures::Scope scope(FPU);
+ int16_t NumSaved = 0;
+ int16_t NumToPush = NumberOfBitsSet(regs);
+
+ addiu(sp, sp, -8 * NumToPush);
+ for (int16_t i = 0; i < kNumRegisters; i++) {
+ if ((regs & (1 << i)) != 0) {
+ sdc1(FPURegister::from_code(i),
+ MemOperand(sp, 8 * (NumToPush - ++NumSaved)));
+ }
+ }
+}
+
+
+void MacroAssembler::MultiPopFPU(RegList regs) {
+ CpuFeatures::Scope scope(FPU);
+ int16_t NumSaved = 0;
+
+ for (int16_t i = 0; i < kNumRegisters; i++) {
+ if ((regs & (1 << i)) != 0) {
+ ldc1(FPURegister::from_code(i),
+ MemOperand(sp, 8 * (NumSaved++)));
+ }
+ }
+ addiu(sp, sp, 8 * NumSaved);
+}
+
+
+void MacroAssembler::MultiPopReversedFPU(RegList regs) {
+ CpuFeatures::Scope scope(FPU);
+ int16_t NumSaved = 0;
+
+ for (int16_t i = kNumRegisters; i > 0; i--) {
+ if ((regs & (1 << i)) != 0) {
+ ldc1(FPURegister::from_code(i),
+ MemOperand(sp, 8 * (NumSaved++)));
+ }
+ }
+ addiu(sp, sp, 8 * NumSaved);
+}
+
+
void MacroAssembler::Ext(Register rt,
Register rs,
uint16_t pos,
Index: src/mips/macro-assembler-mips.h
diff --git a/src/mips/macro-assembler-mips.h
b/src/mips/macro-assembler-mips.h
index
0fcf6f1d8514485cc306736ebe6d32c1bd4660cb..ec0b2029e4e151c5b911e67a7f2ef07e6f08aa79
100644
--- a/src/mips/macro-assembler-mips.h
+++ b/src/mips/macro-assembler-mips.h
@@ -442,6 +442,9 @@ class MacroAssembler: public Assembler {
void MultiPush(RegList regs);
void MultiPushReversed(RegList regs);
+ void MultiPushFPU(RegList regs);
+ void MultiPushReversedFPU(RegList regs);
+
// Lower case push() for compatibility with arch-independent code.
void push(Register src) {
Addu(sp, sp, Operand(-kPointerSize));
@@ -487,6 +490,9 @@ class MacroAssembler: public Assembler {
void MultiPop(RegList regs);
void MultiPopReversed(RegList regs);
+ void MultiPopFPU(RegList regs);
+ void MultiPopReversedFPU(RegList regs);
+
// Lower case pop() for compatibility with arch-independent code.
void pop(Register dst) {
lw(dst, MemOperand(sp, 0));
--
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