http://codereview.chromium.org/8822014/diff/1/src/mips/lithium-codegen-mips.cc File src/mips/lithium-codegen-mips.cc (right): http://codereview.chromium.org/8822014/diff/1/src/mips/lithium-codegen-mips.cc#newcode3000 src/mips/lithium-codegen-mips.cc:3000: From what I can see, you don't need to reserve an additional temp register (and change register allocation in lithium-mips.cc) if you can already take advantage of a double_scratch0(). Or is this double_scratch0() somehow related to kDoubleRegZero? http://codereview.chromium.org/8822014/ -- v8-dev mailing list [email protected] http://groups.google.com/group/v8-dev
This seems to be implemented more complicatedly than necessary. Please
clarify.
- [v8-dev] Re: MIPS: Fixing MathPowHalf on ARM. (issue 8822014) yangguo
