Even if here there is no need for performance, a conditional mov which is
not taken is always faster than an unconditional mov (on well optimized
cores, it will take 0 cycles).


On Thu, Nov 7, 2013 at 9:10 AM, <[email protected]> wrote:

> Thanks for the code review! Responses inline.
>
>
> On 2013/11/07 08:43:23, vincent.belliard.fr wrote:
>
>> https://codereview.chromium.org/62293002/diff/1/src/arm/
>> lithium-codegen-arm.cc
>> File src/arm/lithium-codegen-arm.cc (right):
>>
>
>
> https://codereview.chromium.org/62293002/diff/1/src/arm/
> lithium-codegen-arm.cc#newcode773
>
>> src/arm/lithium-codegen-arm.cc:773: Register scratch = scratch0();
>> May be you can leave the case FLAG_deopt_every_n_times == 1. It really
>>
> generates
>
>> less code for this special case.
>>
>
> I was considering this, but if you want to deoptimize every time, then a
> few
> extra instructions should not matter much. Moreover, I am told this is
> only used
> in fuzzing tests, so performance is not really important here. Or is there
> a use
> case I am not aware of?
>
>
>
> https://codereview.chromium.org/62293002/diff/1/src/arm/
> lithium-codegen-arm.cc#newcode778
>
>> src/arm/lithium-codegen-arm.cc:778: __ mov(scratch, Operand::Zero());
>> You can also make this mov conditional (you must negate the condition).
>>
>
> I am wondering if it would make any difference in performance. If yes,
> which
> way? (Not that it matters, the code is for correctness testing).
>
>
>
> https://codereview.chromium.org/62293002/diff/1/src/arm/
> lithium-codegen-arm.cc#newcode799
>
>> src/arm/lithium-codegen-arm.cc:799: // to use 'msr' and 'mrs'
>> instructions
>>
> here,
>
>> but they are not supported by
>> mrs and msr are available (assembler-arm.h line 1029).
>>
>
> Yes, they are available in the assembler, but our ARM simulator
> (simulator-arm.cc) does not know them,  Simulator::DecodeType01() fails at
> simulator-arm.cc:2247.
>
>
> https://codereview.chromium.org/62293002/
>

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