Reviewers: jbramley, rmcilroy, jarin,
Message:
Spun off bugfix part from https://codereview.chromium.org/222403002/ since
the
optimization is likely to take a different route.
Description:
Fix fixed-point vcvt_f64_s32 immediate value encoding
The (32 - fraction_bits) value should be encoded so that the least
significant bit is set to bit 5 and the four next bits to bits 0-3. Fix
the previously incorrect encoding. This bug did not cause behavioral
issues before, since in existing uses of the function the order of the
bits in the immediate value does not matter, as they are all 1.
BUG=3256
LOG=N
Please review this at https://codereview.chromium.org/223623003/
SVN Base: git://github.com/v8/v8.git@master
Affected files (+9, -8 lines):
M src/arm/assembler-arm.cc
M src/arm/disasm-arm.cc
M src/arm/simulator-arm.cc
M test/cctest/test-assembler-arm.cc
M test/cctest/test-disasm-arm.cc
Index: src/arm/assembler-arm.cc
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index
297cdcc0395819eda41599aad5f138b4671177b2..516d3dd57ac3d7a4a282474b0c687ad576d66f53
100644
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -2827,8 +2827,9 @@ void Assembler::vcvt_f64_s32(const DwVfpRegister dst,
ASSERT(CpuFeatures::IsSupported(VFP3));
int vd, d;
dst.split_code(&vd, &d);
- int i = ((32 - fraction_bits) >> 4) & 1;
- int imm4 = (32 - fraction_bits) & 0xf;
+ int imm5 = 32 - fraction_bits;
+ int i = imm5 & 1;
+ int imm4 = (imm5 >> 1) & 0xf;
emit(cond | 0xE*B24 | B23 | d*B22 | 0x3*B20 | B19 | 0x2*B16 |
vd*B12 | 0x5*B9 | B8 | B7 | B6 | i*B5 | imm4);
}
Index: src/arm/disasm-arm.cc
diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
index
aa8ee22b73a3c4e7b92ea3312e7bd5b3da8bf96a..a0dc05796e59953089f093ccc9fd4a807ce51977
100644
--- a/src/arm/disasm-arm.cc
+++ b/src/arm/disasm-arm.cc
@@ -1272,7 +1272,7 @@ void Decoder::DecodeTypeVFP(Instruction* instr) {
} else if ((instr->Opc2Value() == 0xA) && (instr->Opc3Value() ==
0x3) &&
(instr->Bit(8) == 1)) {
// vcvt.f64.s32 Dd, Dd, #<fbits>
- int fraction_bits = 32 - ((instr->Bit(5) << 4) | instr->Bits(3,
0));
+ int fraction_bits = 32 - (instr->Bit(5) | (instr->Bits(3, 0) <<
1));
Format(instr, "vcvt'cond.f64.s32 'Dd, 'Dd");
out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
", #%d", fraction_bits);
Index: src/arm/simulator-arm.cc
diff --git a/src/arm/simulator-arm.cc b/src/arm/simulator-arm.cc
index
8f7c1e8bb2b740e7884c6ae52c6b867681c9e125..fb3bca902f2eb467662b7ce7f325d7db05d8cf94
100644
--- a/src/arm/simulator-arm.cc
+++ b/src/arm/simulator-arm.cc
@@ -2936,7 +2936,7 @@ void Simulator::DecodeTypeVFP(Instruction* instr) {
} else if ((instr->Opc2Value() == 0xA) && (instr->Opc3Value() ==
0x3) &&
(instr->Bit(8) == 1)) {
// vcvt.f64.s32 Dd, Dd, #<fbits>
- int fraction_bits = 32 - ((instr->Bit(5) << 4) | instr->Bits(3,
0));
+ int fraction_bits = 32 - (instr->Bit(5) | (instr->Bits(3, 0) <<
1));
int fixed_value = get_sinteger_from_s_register(vd * 2);
double divide = 1 << fraction_bits;
set_d_register_from_double(vd, fixed_value / divide);
Index: test/cctest/test-assembler-arm.cc
diff --git a/test/cctest/test-assembler-arm.cc
b/test/cctest/test-assembler-arm.cc
index
9c1c04fe338f52ad478bd61ec306736c5c39ed46..7a3dec5b633a90b8d1c6819e717d3fd97e4d1d9d
100644
--- a/test/cctest/test-assembler-arm.cc
+++ b/test/cctest/test-assembler-arm.cc
@@ -292,9 +292,9 @@ TEST(4) {
__ vstr(d4, r4, OFFSET_OF(T, f));
// Convert from fixed point to floating point.
- __ mov(lr, Operand(1234));
+ __ mov(lr, Operand(2468));
__ vmov(s8, lr);
- __ vcvt_f64_s32(d4, 1);
+ __ vcvt_f64_s32(d4, 2);
__ vstr(d4, r4, OFFSET_OF(T, j));
// Test vabs.
Index: test/cctest/test-disasm-arm.cc
diff --git a/test/cctest/test-disasm-arm.cc b/test/cctest/test-disasm-arm.cc
index
5eff4206ca409c6707a1701a1d7af9d00fc5f6e9..24453bc88ebc683441921488f8dd428267425ac4
100644
--- a/test/cctest/test-disasm-arm.cc
+++ b/test/cctest/test-disasm-arm.cc
@@ -592,8 +592,8 @@ TEST(Vfp) {
"eeb80be0 vcvt.f64.s32 d0, s1");
COMPARE(vcvt_f32_s32(s0, s2),
"eeb80ac1 vcvt.f32.s32 s0, s2");
- COMPARE(vcvt_f64_s32(d0, 1),
- "eeba0bef vcvt.f64.s32 d0, d0, #1");
+ COMPARE(vcvt_f64_s32(d0, 2),
+ "eeba0bcf vcvt.f64.s32 d0, d0, #2");
if (CpuFeatures::IsSupported(VFP32DREGS)) {
COMPARE(vmov(d3, d27),
--
--
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