On Friday 18 February 2011, Wan Mohd Fairuz Wan Ismail wrote: > Hi, > Do cachegrind use the same cache model for different processors? (eg. x86, > armv7-a8, armv7-a9, etc).
Yes. 2 levels (L1 separate for I/D, the other unified), inclusive, synchronous, LRU replacement. Only parameters are adapted to current processor: size, line size, associatvity. If a processor has 3 levels, parameters of L1 and L3 are actually used. This model actually is most near to Intel processors, but it always was just an approximation. Especially it is not simulating the AMD processor exclusive caches (where L2/L3 are victim caches). The idea of this simple model is not to be as near as possible to real hardware, but to highlight common problems of an application regarding cache behavior, such that the code afterwards would run faster on every architecture using caches. Do you see a need for more exact models? Josef > > Thanks, > Kind regards, > ------------------------------------------------------------------------------ The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb _______________________________________________ Valgrind-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/valgrind-users
