Hi all,
In the VEX IR representation of a 'lock' instruction, Valgrind introduces an
CAS instruction.
For example :
lock addw $0x1,0x804b056
to
PUT(60) = 0x8048B38:I32
t19 = LDle:I16(0x804B056:I32) //READ EVENT
t17 = Add16(t19,0x1:I16)
t21 = CASle(0x804B056:I32::t19->t17) //READ AND WRITE EVENTS
t29 = CasCmpNE16(t21,t19)
if (t29) goto {Boring} 0x8048B38:I32
PUT(32) = 0x2:I32
t30 = 16Uto32(t19)
PUT(36) = t30
PUT(40) = 0x1:I32
So for this particular instruction it generates 2 READ events and 1 WRITE
event.
But there would be only 1 READ and 1 WRITE followed by a flush when it runs
on a processor. Am I right?
Regards,
pankaj
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