Hi Philippe, > I have found this relatively new and interesting PDF file : > http://www.altera.com/literature/hb/opencl-sdk/aocl_optimization_guide.pdf > . I'll read it overnight. This is of course for a mid/long-term > perspective, but there are some remarkable points within, for example > (some teasing :D) :
Looks indeed interesting, particularly the implications on hardware synthesis are neat. We have to keep two things in mind for FPGAs: a) OpenCL kernels are static, i.e. they get syntesized to hardware in a separate initial step and cannot be changed/generated during execution. b) Memory bandwidth is limited to what we get for CPUs. Therefore, they won't fly for vector operations, but matrix-matrix-multiplications should work well in terms of FLOPs/Watt. > "The AOC implements local memory in FPGAs very differently than in GPUs. > If your OpenCL kernel contains code to avoid GPU-specific local memory > bank conflicts, remove that code because the AOC generates hardware that > avoids local memory bank conflicts automatically whenever possible." > > Anyway, this is of course not a priority (we don't even have any > hardware to test it), but it might be useful to get some insight on how > Altera's OpenCL is behaving... I'll talk to the Altera guys at the OpenCL workshop, maybe they are willing to provide an evaluation board. Best regards, Karli ------------------------------------------------------------------------------ CenturyLink Cloud: The Leader in Enterprise Cloud Services. Learn Why More Businesses Are Choosing CenturyLink Cloud For Critical Workloads, Development Environments & Everything In Between. Get a Quote or Start a Free Trial Today. http://pubads.g.doubleclick.net/gampad/clk?id=119420431&iu=/4140/ostg.clktrk _______________________________________________ ViennaCL-devel mailing list ViennaCL-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/viennacl-devel
