Has anyone tried this yet? I spent part of July playing with the SRC Saturn1 FPGA for another project. Word of warning: Philippe is correct that portability is a *serious* issue. FPGA compilers take considerably longer to build applications since they need to zero out all gates, then test various layouts of the code to find the best fit in hardware. We're seeing compile times around 40 minutes minimum per kernel. This time grows as a function of the size of the FPGA, so it will only get worse in coming generations. This is why SRC brilliantly offers a "debug mode" where you can build the app in seconds to run an OpenMP application with simulated memory banks.
I think it could be worth considering an SRC port if we utilize both debug and hardware modes. Cheers, -E On Thursday, May 28, 2015, Philippe Tillet <[email protected]> wrote: > Hello, > > Technically, I think that the OpenCL backend of ViennaCL could be patch to > call aoc through a system call. This is not portable enough to be included > in the core, though, but I think that you could use your own fork for this > purpose. > > Philippe > > 2015-05-28 18:18 GMT+02:00 Karl Rupp <[email protected]>: > >> Hi Regina, >> >> > I am an Undergraduate student from Imperial College currently work on a >> > project regarding hardware acceleration with FPGAs using OpenCL. I was >> > wondering if there is anyway to run ViennaCL iterative solvers on an >> > FPGA with Altera SDK for OpenCL? >> >> We have never tried to run ViennaCL on an Altera SDK. The main reason is >> a technical one: As far as I know, the Altera SDK requires to provide >> all OpenCL sources upfront in order to synthesize the hardware. However, >> the OpenCL kernels in ViennaCL are generated at runtime and just-in-time >> compiled. >> >> As far as I can tell, you could extract the relevant OpenCL kernels from >> ViennaCL and use these to synthesize the necessary hardware. On the >> other hand, however, you are very likely limited by memory bandwidth >> anyway, so you won't see any big gains in terms of either performance or >> performance per Watt on an FPGA. The absence of caches might make >> matters worse. >> >> Either way, I'd be happy to hear about the results of your project one >> you're finished. :-) >> >> Best regards, >> Karli >> >> >> >> ------------------------------------------------------------------------------ >> _______________________________________________ >> ViennaCL-support mailing list >> [email protected] >> https://lists.sourceforge.net/lists/listinfo/viennacl-support >> > >
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