On Tue, July 17, 2012 09:04, 王军 wrote: > Sorry,I am chinese.English is not well. > > All ports should be highlight in Verilog's module declaration,But there > some ports are not highlight in this picture. > Example : > RSTn > Sig_rx_sys_cs
That is because the syntax script demands the ports to be upper case ( [A-Z] and your ports contain lower case letters [a-z]). I can't say, whether this is correct or not, but try to use only uppper case letters and the highlighting should apply. regards, Christian -- You received this message from the "vim_use" maillist. Do not top-post! Type your reply below the text you are replying to. For more information, visit http://www.vim.org/maillist.php
