Yes ,you are right! If the letters of port are all upper case,it is highlight. If the letters of port are not all upper case,it is not highlight. Example: RSnT Signal,and so on.
Thank you very much. If I want all letters are highlight,what can I do? Modify Verilog.vim? -----邮件原件----- 发件人: [email protected] [mailto:[email protected]] 代表 Christian Brabandt 发送时间: 2012年7月17日 15:23 收件人: [email protected] 主题: Re: ç”å¤ : some word can't highlight in verilog On Tue, July 17, 2012 09:04, 王军 wrote: > Sorry,I am chinese.English is not well. > > All ports should be highlight in Verilog's module declaration,But > there some ports are not highlight in this picture. > Example : > RSTn > Sig_rx_sys_cs That is because the syntax script demands the ports to be upper case ( [A-Z] and your ports contain lower case letters [a-z]). I can't say, whether this is correct or not, but try to use only uppper case letters and the highlighting should apply. regards, Christian -- You received this message from the "vim_use" maillist. Do not top-post! Type your reply below the text you are replying to. For more information, visit http://www.vim.org/maillist.php -- You received this message from the "vim_use" maillist. Do not top-post! Type your reply below the text you are replying to. For more information, visit http://www.vim.org/maillist.php
