On Mar 3, 2:08 am, yuhong <[email protected]> wrote: > If you are wondering why did the Mac II(x) require PAL SIMMs for 4MB > and higher, answers are in the end of this > technote:http://web.archive.org/web/20040803140105/http://developer.apple.com/... > You will see that it is more correctly 4 Mbits and higher SIMMs, as > well as other details.
Well that was interesting. I've always wondered about those PAL SIMMs. It makes sense that WE_ was a don't care during refreshes for older chips, but not for more recent ones. I don't understand why 1M X 4 chips would have a different row/column structure than 1M X 1 chips though, unless that's just the way things happened. The article seems to imply that 1M X 1 chips are 9row/11col address bits which 1M X 4 chips are 10row/10col. Jeff Walther -- ----- You received this message because you are a member of the Vintage Macs group. The list FAQ is at http://lowendmac.com/lists/vintagemacs.shtml and our netiquette guide is at http://www.lowendmac.com/lists/netiquette.shtml To post to this group, send email to [email protected] To leave this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/vintage-macs Support for older Macs: http://lowendmac.com/services/
