On Mar 3, 1:00 pm, PeterH <[email protected]> wrote: > On Mar 3, 2010, at 10:27 AM, Jeff Walther wrote: > > > I don't understand why 1M X 4 chips would have a different row/column > > structure than 1M X 1 chips though, unless that's just the way things > > happened. The article seems to imply that 1M X 1 chips are 9row/11col > > address bits which 1M X 4 chips are 10row/10col. > > The chip topology is four banks which are operated simultaneously, > with I/O 0 through 3 active at the same time. > > Still, these are row address with *RAS active and column address with > *CAS active, and data valid on the rise of *CAS. > > *RAS refresh uses more power than the method which Apple selected for > these models, but they got bit in the a$$ when the new chips which > disallow *CAS refresh.
Peter, you often have very valuable insights and/or information, but in this case, I can't make heads or tails out of how your response is relevant to the question you quoted. Did you leave out three of four logical steps that lead from A to E? (I.e. left out steps B, C, and D.) I think the first confusing part would be your use of the term "banks". These old FPM chips didn't have banks internally as far as I can tell. I don't think internal banks got going until synchronous DRAM came along, although, perhaps some video RAM chips had banks earlier. Did you mean something else by "bank"? Jeff Walther Jeff Walther -- ----- You received this message because you are a member of the Vintage Macs group. The list FAQ is at http://lowendmac.com/lists/vintagemacs.shtml and our netiquette guide is at http://www.lowendmac.com/lists/netiquette.shtml To post to this group, send email to [email protected] To leave this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/vintage-macs Support for older Macs: http://lowendmac.com/services/
