Hawi display hardware is owned by DCP firmware, so the platform device tree must describe the Qualcomm transport wrapper, firmware display subsystem, power-notify channel, IOMMU contexts, and display graph used by the MSM DRM driver.
Describe the Qualcomm DCP transport and its VirtIO-MMIO child, the IPCC power-notify channel, IOMMU assignments, firmware-visible IOVA range, and DSI display endpoints on Hawi. Enable the DCP display device on the Hawi MTP platform. Assisted-by: LLM Signed-off-by: Jayant Shekhar <[email protected]> --- arch/arm64/boot/dts/qcom/hawi-mtp.dts | 129 ++++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/hawi.dtsi | 40 +++++++++++ 2 files changed, 169 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hawi-mtp.dts b/arch/arm64/boot/dts/qcom/hawi-mtp.dts index c38e5fab7a2c..a27003f69d02 100644 --- a/arch/arm64/boot/dts/qcom/hawi-mtp.dts +++ b/arch/arm64/boot/dts/qcom/hawi-mtp.dts @@ -34,6 +34,18 @@ chosen { stdout-path = "serial0:115200n8"; }; + display_panel_vdd: regulator-display-panel-vdd { + compatible = "regulator-fixed"; + regulator-name = "display-panel-vdd"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + gpio = <&pmd8028_e1_gpios 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + pinctrl-0 = <&sde_disp0_vdd_active>; + pinctrl-names = "default"; + }; + clocks { bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { compatible = "fixed-factor-clock"; @@ -142,6 +154,7 @@ sdcard_vdd_3p0: sdcard-vdd-3p0 { vin-supply = <&vreg_bob1>; }; + }; &apps_rsc { @@ -995,3 +1008,119 @@ &usb_dp_qmpphy { &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; + +&dcp_dsi0 { + panel@0 { + compatible = "novatek,nt37801"; + reg = <0>; + + pinctrl-0 = <&sde_dsi_active &sde_te_active &sde_esync0_suspend + &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active + &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &sde_esync0_suspend + &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active + &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>; + pinctrl-names = "default", "sleep"; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&display_panel_vdd>; + + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + port { + panel_dcp_in: endpoint { + remote-endpoint = <&dcp_intf0_out>; + }; + }; + }; +}; + +&dcp_intf0_out { + remote-endpoint = <&panel_dcp_in>; +}; + +&pmd8028_e1_gpios { + sde_disp0_vdd_active: sde_disp0_vdd_active { + pins = "gpio2"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <2>; + qcom,drive-strength = <2>; + }; +}; + +&pmh0110_d_e0_gpios { + sde_mdp_vsync_p_1p2_active: sde-mdp-vsync-p-1p2-active-state { + pins = "gpio9"; + function = "paired"; + input-disable; + output-enable; + power-source = <2>; /* 1.2v */ + }; + + sde_mdp_vsync_p_1p8_active: sde-mdp-vsync-p-1p8-active-state { + pins = "gpio10"; + function = "paired"; + input-enable; + output-disable; + power-source = <1>; /* 1.8v */ + }; +}; + +&pmh0110_f_e0_gpios { + sde_disp0_rst_1p2_active: sde-disp0-rst-1p2-active-state { + pins = "gpio9"; + function = "paired"; + input-enable; + output-disable; + power-source = <2>; /* 1.2v */ + }; + + sde_disp0_rst_1p8_active: sde-disp0-rst-1p8-active-state { + pins = "gpio10"; + function = "paired"; + input-disable; + output-enable; + power-source = <1>; /* 1.8v */ + }; +}; + +&tlmm { + sde_te_active: sde-te-active-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_esync0_suspend: sde-esync0-suspend-state { + pins = "gpio88"; + function = "mdp_esync0"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio211"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins = "gpio211"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi index 6b0a0ff0faa4..836970cdef71 100644 --- a/arch/arm64/boot/dts/qcom/hawi.dtsi +++ b/arch/arm64/boot/dts/qcom/hawi.dtsi @@ -6841,4 +6841,44 @@ timer { <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + + dcp: virtio@9be8000 { + compatible = "qcom,dcp-virtio"; + reg = <0x0 0x09be8000 0x0 0x1000>; + interrupts-extended = <&intc GIC_ESPI 956 IRQ_TYPE_LEVEL_HIGH>, + <&ipcc 13 5 IRQ_TYPE_EDGE_RISING>; + iommus = <&apps_smmu 0x15a3 0x0>; + iommu-ranges = <0x0 0x84000000 0x0 0x04000000>; + dma-coherent; + mboxes = <&ipcc 13 5>; + mbox-names = "dcp-power-tx"; + + dcp-subsystem { + compatible = "virtio,device34"; + + iommus = <&apps_smmu 0x400 0x2>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dcp_intf0_out: endpoint { + + }; + }; + + }; + + dcp_dsi0: dsi@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; -- 2.43.0
