Keir Fraser wrote:
> Another
> factoid I discovered at the same meeting is that the CPU may cache partial
> page walks. So, for example, just because you 'detach' a page table from a
> page-directory entry, doesn't mean that page table won't be accessed on
> future hardware TLB fills.
>
Do you know if these intermediate TLB entries are level-sensitive? Ie,
if you have a linear pagetable mapping where the pagetable points back
to itself, will that result in multiple TLB entries for the pmd pages
(pmd as pmd, and pmd as pte)?
J
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