On 8/11/06 11:25 pm, "Jeremy Fitzhardinge" <[EMAIL PROTECTED]> wrote:
> Keir Fraser wrote: >> Another >> factoid I discovered at the same meeting is that the CPU may cache partial >> page walks. So, for example, just because you 'detach' a page table from a >> page-directory entry, doesn't mean that page table won't be accessed on >> future hardware TLB fills. >> > > Do you know if these intermediate TLB entries are level-sensitive? Ie, > if you have a linear pagetable mapping where the pagetable points back > to itself, will that result in multiple TLB entries for the pmd pages > (pmd as pmd, and pmd as pte)? I think so. I can't think why the CPU would bother to disallow this. It does mean you have to be careful when changing page-directory entries that your linear mapping (if you have one) doesn't go stale. -- Keir _______________________________________________ Virtualization mailing list [email protected] https://lists.osdl.org/mailman/listinfo/virtualization
