On Sat, Mar 03, 2001 at 02:52:30PM -0800, Bill Broadley wrote:
> One thing rolling around the newest gcc's is SSE support, which means
> that the compiler replaces the mostly broken x87 FP stack with the SSE
> instructions that allow more then one fp operation per cycle.
>
> Apparently increases of 100-200% have been seen, pretty
> cool stuff.
>
> AMD has announced future athlons (palamino) will include SSE support.
Sorry for the dumb question, but what is SSE?
And, by x87 FP stack, do you mean the x86 chips 87 Floating Point
coprocessor? And it only does one FP instruction per cycle (cause I
thought it did more around the time of 486 or early pentium chips)?
