[webkit-changes] [194354] trunk/Source/JavaScriptCore

Mon, 21 Dec 2015 15:40:34 -0800

Title: [194354] trunk/Source/_javascript_Core
Revision
194354
Author
[email protected]
Date
2015-12-21 15:40:36 -0800 (Mon, 21 Dec 2015)

Log Message

B3 should be able to compile Store16
https://bugs.webkit.org/show_bug.cgi?id=152493

Reviewed by Saam Barati.

This adds comprehensive Store16 support to our assembler, Air, and B3->Air lowering.

* assembler/MacroAssemblerX86Common.h:
(JSC::MacroAssemblerX86Common::store16):
* assembler/X86Assembler.h:
(JSC::X86Assembler::movb_rm):
(JSC::X86Assembler::movw_rm):
* b3/B3LowerToAir.cpp:
(JSC::B3::Air::LowerToAir::lower):
* b3/air/AirOpcode.opcodes:
* b3/testb3.cpp:
(JSC::B3::testStorePartial8BitRegisterOnX86):
(JSC::B3::testStore16Arg):
(JSC::B3::testStore16Imm):
(JSC::B3::testTrunc):
(JSC::B3::run):

Modified Paths

Diff

Modified: trunk/Source/_javascript_Core/ChangeLog (194353 => 194354)


--- trunk/Source/_javascript_Core/ChangeLog	2015-12-21 23:32:57 UTC (rev 194353)
+++ trunk/Source/_javascript_Core/ChangeLog	2015-12-21 23:40:36 UTC (rev 194354)
@@ -1,5 +1,29 @@
 2015-12-21  Filip Pizlo  <[email protected]>
 
+        B3 should be able to compile Store16
+        https://bugs.webkit.org/show_bug.cgi?id=152493
+
+        Reviewed by Saam Barati.
+
+        This adds comprehensive Store16 support to our assembler, Air, and B3->Air lowering.
+
+        * assembler/MacroAssemblerX86Common.h:
+        (JSC::MacroAssemblerX86Common::store16):
+        * assembler/X86Assembler.h:
+        (JSC::X86Assembler::movb_rm):
+        (JSC::X86Assembler::movw_rm):
+        * b3/B3LowerToAir.cpp:
+        (JSC::B3::Air::LowerToAir::lower):
+        * b3/air/AirOpcode.opcodes:
+        * b3/testb3.cpp:
+        (JSC::B3::testStorePartial8BitRegisterOnX86):
+        (JSC::B3::testStore16Arg):
+        (JSC::B3::testStore16Imm):
+        (JSC::B3::testTrunc):
+        (JSC::B3::run):
+
+2015-12-21  Filip Pizlo  <[email protected]>
+
         Unreviewed, remove highBitsAreZero(), it's unused.
 
         * b3/B3LowerToAir.cpp:

Modified: trunk/Source/_javascript_Core/assembler/MacroAssemblerX86Common.h (194353 => 194354)


--- trunk/Source/_javascript_Core/assembler/MacroAssemblerX86Common.h	2015-12-21 23:32:57 UTC (rev 194353)
+++ trunk/Source/_javascript_Core/assembler/MacroAssemblerX86Common.h	2015-12-21 23:40:36 UTC (rev 194354)
@@ -821,7 +821,26 @@
         m_assembler.movw_rm(src, address.offset, address.base, address.index, address.scale);
     }
 
+    void store16(RegisterID src, Address address)
+    {
+#if CPU(X86)
+        // On 32-bit x86 we can only store from the first 4 registers;
+        // esp..edi are mapped to the 'h' registers!
+        if (src >= 4) {
+            // Pick a temporary register.
+            RegisterID temp = getUnusedRegister(address);
 
+            // Swap to the temporary register to perform the store.
+            swap(src, temp);
+            m_assembler.movw_rm(temp, address.offset, address.base);
+            swap(src, temp);
+            return;
+        }
+#endif
+        m_assembler.movw_rm(src, address.offset, address.base);
+    }
+
+
     // Floating-point operation:
     //
     // Presently only supports SSE, not x87 floating point.

Modified: trunk/Source/_javascript_Core/assembler/X86Assembler.h (194353 => 194354)


--- trunk/Source/_javascript_Core/assembler/X86Assembler.h	2015-12-21 23:32:57 UTC (rev 194353)
+++ trunk/Source/_javascript_Core/assembler/X86Assembler.h	2015-12-21 23:40:36 UTC (rev 194354)
@@ -1550,6 +1550,12 @@
         m_formatter.oneByteOp8(OP_MOV_EbGb, src, base, index, scale, offset);
     }
 
+    void movw_rm(RegisterID src, int offset, RegisterID base)
+    {
+        m_formatter.prefix(PRE_OPERAND_SIZE);
+        m_formatter.oneByteOp8(OP_MOV_EvGv, src, base, offset);
+    }
+
     void movw_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
     {
         m_formatter.prefix(PRE_OPERAND_SIZE);

Modified: trunk/Source/_javascript_Core/b3/B3LowerToAir.cpp (194353 => 194354)


--- trunk/Source/_javascript_Core/b3/B3LowerToAir.cpp	2015-12-21 23:32:57 UTC (rev 194353)
+++ trunk/Source/_javascript_Core/b3/B3LowerToAir.cpp	2015-12-21 23:40:36 UTC (rev 194354)
@@ -1729,6 +1729,12 @@
             return;
         }
 
+        case B3::Store16: {
+            Value* valueToStore = m_value->child(0);
+            m_insts.last().append(createStore(Air::Store16, valueToStore, addr(m_value)));
+            return;
+        }
+
         case Trunc: {
             ASSERT(tmp(m_value->child(0)) == tmp(m_value));
             return;

Modified: trunk/Source/_javascript_Core/b3/air/AirOpcode.opcodes (194353 => 194354)


--- trunk/Source/_javascript_Core/b3/air/AirOpcode.opcodes	2015-12-21 23:32:57 UTC (rev 194353)
+++ trunk/Source/_javascript_Core/b3/air/AirOpcode.opcodes	2015-12-21 23:40:36 UTC (rev 194354)
@@ -422,6 +422,10 @@
     Addr, Tmp
     Index, Tmp
 
+Store16 U:G:16, D:G:16
+    Tmp, Index
+    Tmp, Addr
+
 Compare32 U:G:32, U:G:32, U:G:32, ZD:G:32
     RelCond, Tmp, Tmp, Tmp
     RelCond, Tmp, Imm, Tmp

Modified: trunk/Source/_javascript_Core/b3/testb3.cpp (194353 => 194354)


--- trunk/Source/_javascript_Core/b3/testb3.cpp	2015-12-21 23:32:57 UTC (rev 194353)
+++ trunk/Source/_javascript_Core/b3/testb3.cpp	2015-12-21 23:40:36 UTC (rev 194354)
@@ -4044,6 +4044,84 @@
     CHECK(!storage);
 }
 
+void testStore16Arg()
+{
+    { // Direct addressing.
+        Procedure proc;
+        BasicBlock* root = proc.addBlock();
+
+        Value* value = root->appendNew<Value>(proc, Trunc, Origin(),
+            root->appendNew<ArgumentRegValue>(proc, Origin(), GPRInfo::argumentGPR0));
+        Value* address = root->appendNew<ArgumentRegValue>(proc, Origin(), GPRInfo::argumentGPR1);
+
+        root->appendNew<MemoryValue>(proc, Store16, Origin(), value, address);
+        root->appendNew<ControlValue>(proc, Return, Origin(), value);
+
+        int16_t storage = -1;
+        CHECK(compileAndRun<int64_t>(proc, 42, &storage) == 42);
+        CHECK(storage == 42);
+    }
+
+    { // Indexed addressing.
+        Procedure proc;
+        BasicBlock* root = proc.addBlock();
+
+        Value* value = root->appendNew<Value>(proc, Trunc, Origin(),
+            root->appendNew<ArgumentRegValue>(proc, Origin(), GPRInfo::argumentGPR0));
+        Value* base = root->appendNew<ArgumentRegValue>(proc, Origin(), GPRInfo::argumentGPR1);
+        Value* offset = root->appendNew<ArgumentRegValue>(proc, Origin(), GPRInfo::argumentGPR2);
+        Value* displacement = root->appendNew<Const64Value>(proc, Origin(), -1);
+
+        Value* baseDisplacement = root->appendNew<Value>(proc, Add, Origin(), displacement, base);
+        Value* address = root->appendNew<Value>(proc, Add, Origin(), baseDisplacement, offset);
+
+        root->appendNew<MemoryValue>(proc, Store16, Origin(), value, address);
+        root->appendNew<ControlValue>(proc, Return, Origin(), value);
+
+        int8_t storage = -1;
+        CHECK(compileAndRun<int64_t>(proc, 42, &storage, 1) == 42);
+        CHECK(storage == 42);
+    }
+}
+
+void testStore16Imm()
+{
+    { // Direct addressing.
+        Procedure proc;
+        BasicBlock* root = proc.addBlock();
+
+        Value* value = root->appendNew<Const32Value>(proc, Origin(), 42);
+        Value* address = root->appendNew<ArgumentRegValue>(proc, Origin(), GPRInfo::argumentGPR0);
+
+        root->appendNew<MemoryValue>(proc, Store16, Origin(), value, address);
+        root->appendNew<ControlValue>(proc, Return, Origin(), value);
+
+        int16_t storage = -1;
+        CHECK(compileAndRun<int64_t>(proc, &storage) == 42);
+        CHECK(storage == 42);
+    }
+
+    { // Indexed addressing.
+        Procedure proc;
+        BasicBlock* root = proc.addBlock();
+
+        Value* value = root->appendNew<Const32Value>(proc, Origin(), 42);
+        Value* base = root->appendNew<ArgumentRegValue>(proc, Origin(), GPRInfo::argumentGPR0);
+        Value* offset = root->appendNew<ArgumentRegValue>(proc, Origin(), GPRInfo::argumentGPR1);
+        Value* displacement = root->appendNew<Const64Value>(proc, Origin(), -1);
+
+        Value* baseDisplacement = root->appendNew<Value>(proc, Add, Origin(), displacement, base);
+        Value* address = root->appendNew<Value>(proc, Add, Origin(), baseDisplacement, offset);
+
+        root->appendNew<MemoryValue>(proc, Store16, Origin(), value, address);
+        root->appendNew<ControlValue>(proc, Return, Origin(), value);
+
+        int16_t storage = -1;
+        CHECK(compileAndRun<int64_t>(proc, &storage, 1) == 42);
+        CHECK(storage == 42);
+    }
+}
+
 void testTrunc(int64_t value)
 {
     Procedure proc;
@@ -9437,6 +9515,8 @@
     RUN(testStore8Arg());
     RUN(testStore8Imm());
     RUN(testStorePartial8BitRegisterOnX86());
+    RUN(testStore16Arg());
+    RUN(testStore16Imm());
     RUN(testTrunc((static_cast<int64_t>(1) << 40) + 42));
     RUN(testAdd1(45));
     RUN(testAdd1Ptr(51));

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