R. Timothy Edwards <rtedwar...@gmail.com> wrote: > For other netlist formats like SPICE, you could just remove the > "spice:" info label from the symbol and it would no longer be a > netlist element. But PCB netlists are output by net, not by instance, > so I'm not sure that method works. > > There is also a checkbox for "netlistable instance" under the Netlist > menu. This strikes me as more likely to work for PCB netlists, but > you'd have to try it.
This one was caused by my tap element not having a '% trivial' comment. Before I figured it out, I did look into the netlistable instance flag, but the menu option didn't appear to do anything. I added the '% nonetwork' flag to the tap element, but then the bus signals weren't connected at all :) I got what I asked for. There is some code in files.c to read/write the not netlistable flag as '/nn', but again, I'm not sure what it is used for. > > Another small detail I noticed: the bus numbering in the netlist still > > starts from 0 and increases even though I labeled my bus > > a2data(7:0). The connectivity is correct, though it may be confusing > > when laying out the pcb. > > I haven't worked on the bus handling code for ages. You'd need to > supply an example schematic and tell me how you expect it to look in > the netlist output so I can figure out how the underlying issue should > be approached. I've attached a small schematic and netlist. There is an 8 bit bus declared as 'data(7:0)' in the global label and the tap elements. The jumper8 elements assign d0 to pin 1, d1 to pin 2, and so on. Here is the netlist: data(7) J2-1 J1-1 data(6) J2-2 J1-2 data(5) J2-3 J1-3 data(4) J2-4 J1-4 data(3) J2-5 J1-5 data(2) J2-6 J1-6 data(1) J2-7 J1-7 data(0) J2-8 J1-8 I would expect this: data(0) J2-1 J1-1 data(1) J2-2 J1-2 data(2) J2-3 J1-3 data(3) J2-4 J1-4 data(4) J2-5 J1-5 data(5) J2-6 J1-6 data(6) J2-7 J1-7 data(7) J2-8 J1-8 I get the expected behavior if I modify the tap elements to use 'data(0:7)' instead of 'data(7:0)'. This workaround is fine for me, but I mentioned it because this text from http://opencircuitdesign.com/xcircuit/tutorial/tutorial2.html#Task17 seems to indicate that either order is ok. >>> Virtually all EDA tools recognize buses by some obvious representation like >>> >>> busname(x:y) >>> >>> which indicates a bus of (y - x + 1) separate nets that is drawn with a >>> single wire. In a netlist format that doesn't allow buses, this bus will be >>> expanded into its individual nets: >>> >>> busname(x) >>> busname(x + 1) >>> busname(x + 2) >>> ... >>> busname(y) >>> >>> Note that the above expansion assumes that x < y, but that need not be the >>> case. -- Daniel
data(7) J2-1 J1-1 data(6) J2-2 J1-2 data(5) J2-3 J1-3 data(4) J2-4 J1-4 data(3) J2-5 J1-5 data(2) J2-6 J1-6 data(1) J2-7 J1-7 data(0) J2-8 J1-8
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