On Tue, 29 Apr 2025, Mykyta Poturai wrote: > From: Rahul Singh <rahul.si...@arm.com> > > When ITS is enabled and PCI devices that are behind an SMMU generate an > MSI interrupt, SMMU fault will be observed as there is currently no > mapping in p2m table for the ITS translation register (GITS_TRANSLATER). > > A mapping is required in the iommu page tables so that the device can > generate the MSI interrupt writing to the GITS_TRANSLATER register. > > The GITS_TRANSLATER register is a 32-bit register, and there is nothing > else in a page containing it, so map that page. > > Add new host_addr parameter to vgic_v3_its_init_virtual to prepare the > foundation for DomU MSI support where guest doorbell address can differ > for the host's. Note that the 1:1 check in arm_iommu_map_page remains > for now, as virtual ITSes are currently only created for hwdom where the > doorbell mapping is always 1:1. > > Signed-off-by: Rahul Singh <rahul.si...@arm.com> > Signed-off-by: Stewart Hildebrand <stewart.hildebr...@amd.com> > Signed-off-by: Mykyta Poturai <mykyta_potu...@epam.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
