>> + switch ( attr_idx )
>> + {
>> + case MT_NORMAL_NC:
>> + /*
>> + * ARM ARM: Overlaying the shareability attribute (DDI
>> + * 0406C.b B3-1376 to 1377)
> It's a bit odd to provide here the manual for Armv7.
> Also, our general advice is to use the latest revision.
I’m thinking about restructuring in this way:
switch ( attr_idx )
{
/*
* ARM ARM: Shareable, Inner Shareable, and Outer Shareable Normal memory
* (DDI 0487L.a B2.10.1.1.1 Note section):
*
* Because all data accesses to Non-cacheable locations are data coherent
* to all observers, Non-cacheable locations are always treated as Outer
* Shareable
*
* ARM ARM: Device memory (DDI 0487L.a B2.10.2)
*
* All of these memory types have the following properties:
* [...]
* - Data accesses to memory locations are coherent for all observers in
* the system, and correspondingly are treated as being Outer Shareable
*/
case MT_NORMAL_NC:
/* Fall through */
case MT_DEVICE_nGnRnE:
/* Fall through */
case MT_DEVICE_nGnRE:
prbar.reg.sh = LPAE_SH_OUTER;
break;
default:
/* Xen mappings are SMP coherent */
prbar.reg.sh = LPAE_SH_INNER;
break;
}
what do you think? It will have the fall through comment and will also explain
the LPAE_SH_OUTER value set
for both normal memory nc and device memory.
Please let me know.
Cheers,
Luca
