On ARMv8 architecture SMC instruction from aarch32 state can be conditional.
(ARM DDI 0487A.k page D7-1949)
Thus, we should not skip it while checking HSR.EC value.
For this type of exception special coding of HSR.ISS is used. There is
additional flag (CCKNOWNPASS) to check before perfoming standard handling
of CCVALID and COND fields.
Because we can't distinguish ARMv7 from aarch32 state, we will always
check CCKNOWNPASS field. On ARMv7 it will be read as 0
(ARM DDI 0406C.c page B3-1431), so there will be no problem.
Signed-off-by: Volodymyr Babchuk <volodymyr_babc...@epam.com>
- Added references to the ARM manuals.
- Moved code from under #ifdef CONFIG_ARM_64
- Added comment with rationale for this
xen/arch/arm/traps.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index eae2212..384219d 100644
@@ -1716,8 +1716,24 @@ static int check_conditional_instr(struct cpu_user_regs
unsigned long cpsr, cpsr_cond;
+ * SMC32 instruction case is very special. Under SMC32 we mean
+ * SMC instruction on ARMv7 or SMC instruction originating from
+ * aarch32 state on ARMv8.
+ * On ARMv7 it is uncoditional (ARM DDI 0406C.c page B3-1431),
+ * but is conditional on ARMv8 (ARM DDI 0487A.k page D7-1949).
+ * Problem is that we can't determine if XEN is running on
+ * ARMv7 on ARMv8 in aarch32 mode. Fortunately, while running
+ * on ARMv7 all conditonal bits of HSR will read as 0
+ * (ARM DDI 0406C.c page B3-1431).
+ * This includes CCKNOWNPASS bit of HSR. Thereby we will be okay,
+ * if we'll check that bit.
+ if (hsr.ec == HSR_EC_SMC32 && hsr.smc32.ccknownpass == 0)
+ return 1;
/* Unconditional Exception classes */
- if ( hsr.ec == HSR_EC_UNKNOWN || hsr.ec >= 0x10 )
+ if ( hsr.ec == HSR_EC_UNKNOWN || (hsr.ec >= 0x10 && hsr.ec !=
/* Check for valid condition in hsr */
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