---
 xen/arch/x86/cpu/intel.c    | 3 ++-
 xen/include/asm-x86/cpuid.h | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 7b60aaa..95c8e14 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -27,19 +27,20 @@ static bool_t __init probe_intel_cpuid_faulting(void)
                return 0;
 
        expected_levelling_cap |= LCAP_faulting;
        levelling_caps |=  LCAP_faulting;
        __set_bit(X86_FEATURE_CPUID_FAULTING, boot_cpu_data.x86_capability);
        return 1;
 }
 
+DEFINE_PER_CPU(bool_t, cpuid_faulting_enabled);
+
 static void set_cpuid_faulting(bool_t enable)
 {
-       static DEFINE_PER_CPU(bool_t, cpuid_faulting_enabled);
        bool_t *this_enabled = &this_cpu(cpuid_faulting_enabled);
        uint32_t hi, lo;
 
        ASSERT(cpu_has_cpuid_faulting);
 
        if (*this_enabled == enable)
                return;
 
diff --git a/xen/include/asm-x86/cpuid.h b/xen/include/asm-x86/cpuid.h
index 8e3f639..af8eb9d 100644
--- a/xen/include/asm-x86/cpuid.h
+++ b/xen/include/asm-x86/cpuid.h
@@ -59,16 +59,19 @@ struct cpuidmasks
 };
 
 /* Per CPU shadows of masking MSR values, for lazy context switching. */
 DECLARE_PER_CPU(struct cpuidmasks, cpuidmasks);
 
 /* Default masking MSR values, calculated at boot. */
 extern struct cpuidmasks cpuidmask_defaults;
 
+/* Whether or not cpuid faulting is available for the current domain. */
+DECLARE_PER_CPU(bool_t, cpuid_faulting_enabled);
+
 #endif /* __ASSEMBLY__ */
 #endif /* !__X86_CPUID_H__ */
 
 /*
  * Local variables:
  * mode: C
  * c-file-style: "BSD"
  * c-basic-offset: 4

base-commit: 71b8b46111219a2f83f4f9ae06ac5409744ea86e
-- 
2.10.1


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