CPUs having no model-specific LBRs don't implement DEBUGCTLMSR.LBR
and LBRs can only be enabled if the processor supports architectural
LBRs.
Split the logic to enable LBRs into a separate function and expand the
logic to also implement support for arch LBRs if model-specific LBRs
are not supported.
Signed-off-by: Roger Pau Monné <roger....@citrix.com>
---
xen/arch/x86/include/asm/msr-index.h | 18 +++++++++++++
xen/arch/x86/traps.c | 29 ++++++++++++++++++---
xen/include/public/arch-x86/cpufeatureset.h | 1 +
3 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/include/asm/msr-index.h
b/xen/arch/x86/include/asm/msr-index.h
index 3e038db618..7b08e1804b 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -139,6 +139,24 @@
#define PASID_PASID_MASK 0x000fffff
#define PASID_VALID (_AC(1, ULL) << 31)
+#define MSR_ARCH_LBR_CTL 0x000014ce
+#define ARCH_LBR_CTL_LBREN (_AC(1, ULL) << 0)
+#define ARCH_LBR_CTL_OS (_AC(1, ULL) << 1)
+#define ARCH_LBR_CTL_COND (_AC(1, ULL) << 16)
+#define ARCH_LBR_CTL_NEAR_REL_JMP (_AC(1, ULL) << 17)
+#define ARCH_LBR_CTL_NEAR_IND_JMP (_AC(1, ULL) << 18)
+#define ARCH_LBR_CTL_NEAR_REL_CALL (_AC(1, ULL) << 19)
+#define ARCH_LBR_CTL_NEAR_IND_CALL (_AC(1, ULL) << 20)
+#define ARCH_LBR_CTL_NEAR_RET (_AC(1, ULL) << 21)
+#define ARCH_LBR_CTL_OTHER_BRANCH (_AC(1, ULL) << 22)
+#define ARCH_LBR_CTL_RECORD_ALL (ARCH_LBR_CTL_COND | \
+ ARCH_LBR_CTL_NEAR_REL_JMP | \
+ ARCH_LBR_CTL_NEAR_IND_JMP | \
+ ARCH_LBR_CTL_NEAR_REL_CALL | \
+ ARCH_LBR_CTL_NEAR_IND_CALL | \
+ ARCH_LBR_CTL_NEAR_RET | \
+ ARCH_LBR_CTL_OTHER_BRANCH)
+
#define MSR_EFER 0xc0000080 /* Extended Feature
Enable Register */
#define EFER_SCE (_AC(1, ULL) << 0) /* SYSCALL
Enable */
#define EFER_LME (_AC(1, ULL) << 8) /* Long Mode
Enable */
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 4c38f6c015..133348d9f9 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1963,6 +1963,29 @@ void do_device_not_available(struct cpu_user_regs *regs)
#endif
}
+static bool enable_lbr(void)
+{
+ uint64_t debugctl;
+
+ wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
+ rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
+ if ( !(debugctl & IA32_DEBUGCTLMSR_LBR) )
+ {
+ /*
+ * CPUs with no model-specific LBRs always return DEBUGCTLMSR.LBR
+ * == 0, attempt to set arch LBR if available.
+ */
+ if ( !boot_cpu_has(X86_FEATURE_ARCH_LBR) )
+ return false;
+
+ /* Note that LASTINT{FROMIP,TOIP} matches LER_{FROM_IP,TO_IP} */
+ wrmsrl(MSR_ARCH_LBR_CTL, ARCH_LBR_CTL_LBREN | ARCH_LBR_CTL_OS |
+ ARCH_LBR_CTL_RECORD_ALL);
+ }
+
+ return true;
+}
+
void do_debug(struct cpu_user_regs *regs)
{
unsigned long dr6;
@@ -1997,7 +2020,7 @@ void do_debug(struct cpu_user_regs *regs)
/* #DB automatically disabled LBR. Reinstate it if debugging Xen. */
if ( cpu_has_xen_lbr )
- wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
+ enable_lbr();
if ( !guest_mode(regs) )
{
@@ -2179,8 +2202,8 @@ void percpu_traps_init(void)
if ( !ler_msr && (ler_msr = calc_ler_msr()) )
setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
- if ( cpu_has_xen_lbr )
- wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
+ if ( cpu_has_xen_lbr && !enable_lbr() )
+ printk(XENLOG_ERR "CPU#%u: failed to enable LBR\n",
smp_processor_id());
}
void __init init_idt_traps(void)
diff --git a/xen/include/public/arch-x86/cpufeatureset.h
b/xen/include/public/arch-x86/cpufeatureset.h
index 9cee4b439e..cd6409f9f3 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -280,6 +280,7 @@ XEN_CPUFEATURE(RTM_ALWAYS_ABORT, 9*32+11) /*! June 2021 TSX
defeaturing in micro
XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */
XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*A SERIALIZE insn */
XEN_CPUFEATURE(TSXLDTRK, 9*32+16) /*a TSX load tracking suspend/resume
insns */
+XEN_CPUFEATURE(ARCH_LBR, 9*32+19) /* Intel ARCH LBR */
XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */
XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by
Intel) */
XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */
--
2.36.0
