> On 19 Jun 2023, at 18:01, Julien Grall <jul...@xen.org> wrote:
>
> From: Julien Grall <jgr...@amazon.com>
>
> Per the Arm Arm (ARM DDI 0406C.d A3.8.3):
>
> "The DMB and DSB memory barriers affect reads and writes to the memory
> system generated by load/store instructions and data or unified cache
> maintenance operations being executed by the processor. Instruction
> fetches or accesses caused by a hardware translation table access are
> not explicit accesses."
>
> In setup_fixmap(), we write the fixmap area and may be used soon after,
> for instance, to write to the UART. IOW, there could be hardware
> translation table access. So we need to ensure the 'dsb' has completed
> before continuing. Therefore add an 'isb'.
>
> Fixes: e79999e587d7 ("xen/arm32: head: Remove 1:1 mapping as soon as it is
> not used")
> Signed-off-by: Julien Grall <jgr...@amazon.com>
> ---
Hi Julien,
Yeah makes sense!
Reviewed-by: Luca Fancellu <luca.fance...@arm.com>
