On 18/11/2024 9:13 am, Tu Dinh wrote: > On 18/11/2024 09:52, Jan Beulich wrote: >> Looking over just the files touched: No change to XSAVE logic at all? > XSAVE is hidden behind a new IA32_XSS bit. I'll try to implement that next.
It's rather more severe than that. Without XSAVE support, Xen can't context-switch the LBR state when vCPUs are scheduled in and out. (In patch 4 you seem to have copied the legacy way, which is extremely expensive.) Architecturally, ARCH_LBR depends on XSAVES so OSes can context switch it easily(ish) per thread. There's also a reason why we haven't got this working yet. There are a couple of areas of prerequisite work which need addressing before XSS can be enabled properly. If you're willing to tackle this, then I can explain what needs doing, and in roughly which order. ~Andrew
