Hi Luca,
On 13/05/2025 09:45, Luca Fancellu wrote:
From: Penny Zheng <penny.zh...@arm.com>
Introduce pr_t typedef which is a structure having the prbar
and prlar members, each being structured as the registers of
the AArch64 Armv8-R architecture.
Signed-off-by: Penny Zheng <penny.zh...@arm.com>
Signed-off-by: Wei Chen <wei.c...@arm.com>
Signed-off-by: Luca Fancellu <luca.fance...@arm.com>
Acked-by: Julien Grall <jgr...@amazon.com>
Cheers,
---
Changes in v5:
- Given some comments on the page.h flags, I had to rework some
fields here to better match the flags usage and avoid duplication
Changes in v4:
- Fixed typos, changed name for reserved bitfields, add emacs bits
to arm64/mpu.h.
Now base and limit are 42 bits as we consider FEAT_LPA disabled,
since we support max 1TB of memory.
Moved data structure in commit that uses it
---
xen/arch/arm/include/asm/arm64/mpu.h | 52 ++++++++++++++++++++++++++++
xen/arch/arm/include/asm/mpu.h | 4 +++
2 files changed, 56 insertions(+)
create mode 100644 xen/arch/arm/include/asm/arm64/mpu.h
diff --git a/xen/arch/arm/include/asm/arm64/mpu.h
b/xen/arch/arm/include/asm/arm64/mpu.h
new file mode 100644
index 000000000000..d3c055a2e53b
--- /dev/null
+++ b/xen/arch/arm/include/asm/arm64/mpu.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ARM_ARM64_MPU_H__
+#define __ARM_ARM64_MPU_H__
+
+#ifndef __ASSEMBLY__
+
+/* Protection Region Base Address Register */
+typedef union {
+ struct __packed {
+ unsigned long xn_0:1; /* Execute-Never XN[0] */
+ unsigned long xn:1; /* Execute-Never XN[1] */
+ unsigned long ap_0:1; /* Access Permission AP[0] */
+ unsigned long ro:1; /* Access Permission AP[1] */
+ unsigned long sh:2; /* Shareability */
+ unsigned long base:42; /* Base Address */
+ unsigned long res0:16; /* RES0 */
+ } reg;
+ uint64_t bits;
+} prbar_t;
+
+/* Protection Region Limit Address Register */
+typedef union {
+ struct __packed {
+ unsigned long en:1; /* Region enable */
+ unsigned long ai:3; /* Memory Attribute Index */
+ unsigned long ns:1; /* Not-Secure */
+ unsigned long res0:1; /* RES0 */
+ unsigned long limit:42; /* Limit Address */
+ unsigned long res1:16; /* RES0 */
+ } reg;
+ uint64_t bits;
+} prlar_t;
+
+/* MPU Protection Region */
+typedef struct {
+ prbar_t prbar;
+ prlar_t prlar;
+} pr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARM_ARM64_MPU_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h
index d4ec4248b62b..bb83f5a5f580 100644
--- a/xen/arch/arm/include/asm/mpu.h
+++ b/xen/arch/arm/include/asm/mpu.h
@@ -6,6 +6,10 @@
#ifndef __ARM_MPU_H__
#define __ARM_MPU_H__
+#if defined(CONFIG_ARM_64)
+# include <asm/arm64/mpu.h>
+#endif
+
#define MPU_REGION_SHIFT 6
#define MPU_REGION_ALIGN (_AC(1, UL) << MPU_REGION_SHIFT)
#define MPU_REGION_MASK (~(MPU_REGION_ALIGN - 1))
--
Julien Grall
