Sorry for the late reply. On Sat, Jul 7, 2018 at 2:25 PM, Julien Grall <julien.gr...@arm.com> wrote:
> Hello, > > On 07/07/2018 08:32 PM, Saeed Mirzamohammadi wrote: > >> Thanks for your detailed reply. >> >> On Fri, Jul 6, 2018 at 6:13 AM, Julien Grall <julien.gr...@arm.com >> <mailto:julien.gr...@arm.com>> wrote: >> >> >> >> On 06/07/18 04:51, Saeed Mirzamohammadi wrote: >> >> Hi, >> >> >> Hello, >> >> I'm trying to route all the physical interrupts to the guest >> domain rather than being trapped in the Xen. I would like to >> know what is the right way to do that? >> >> >> May I ask what is your use case for that? If you route interrupts to >> the guest, Xen will not receive vital interrupt such as the timer, >> UART, SMMU interrupts, maintenance interrupt.... >> >> I only have one guest domain. So, I'm trying to make Xen transparent to >> avoid any extra overhead caused by trapping interrupts. >> > > Do you include Dom0 in your "one guest domain"? If so, may I ask what is > your end goal? Why not booting the OS on baremetal? > > Yes, I only have the Dom0 domain and no DomU. My end goal is to make Xen transparent to the interrupts but have control over the memory management and be able to create another domain (like a driver domain) on-demand whenever I need it. > But I still need Xen for my own hypercalls. I don't need the timer cause I >> pinned and don't need any vcpu scheduler. >> > > Well, Xen still needs interrupts for other things like UART and SMMU. It > also needs interrupts to IPI other pCPU such as for softirq, unblocking > another vCPU (waiting on an event for instance)... I don't think you can > discard interrupts that easily in Xen without some cooperation with the > guest. > > Let's imagine Xen IPIs another pCPU. If interrupts are routed to your > guest, this guest will receive the IPIs and will not understand what to do. My end goal is that all the IPIs are handled in the guest like when it is on baremetal. > > > Based on my understanding, I can only disable the interrupts on ARM all >> together using the HCR_EL2 register and we can't pick one interrupt to not >> trap, right? >> > > Depends on your interrupts controller. On GICv4, you will be able to > directly injected some LPIs (i.e MSI). > > > >> >> >> I know that HCR_IMO bit in the HCR_EL2 register is supposed to >> be for routing the interrupts to the guest (Routing to EL1 >> instead of EL2). >> link to the datasheet: >> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc. >> ddi0500d/CIHJHAAG.html >> <http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc >> .ddi0500d/CIHJHAAG.html> >> >> So, I have tried doing the following in >> the leave_hypervisor_tail. I run a simple hypercall and do the >> following lines before return (which is I guess the last point >> of exit to the guest from hypervisor): >> --------------------- >> /current->arch.hcr_el2 &= ~HCR_IMO;/ >> /WRITE_SYSREG(current->arch.hcr_el2, HCR_EL2);/ >> /isb();/ >> /----------------------/ >> / >> / >> /It looks like to be doing it right for all >> thevcpus butgets stuck after return from leave_hypervisor_tail >> for the lastvcpu. >> >> >> What do you mean by stuck? Do you see any logs? >> >> It's hung with no log. >> >> >> HCR_EL2.IMO unset means the interrupt will get signaled to EL1. It >> does not affect how interrupt will get read (e.g IAR). >> >> Which interrupt controller are you using? >> >> I'm using a GICv2. >> >> In case of GICv2, Xen is re-mapping GICC to GICV. So when the guest >> is reading IAR, it will read the interrupts from the LRs. Not the >> physical interface. >> >> So, in the case of GICv2, we can't route them cause Xen is the one that >> is updating the LRs and guest is reading from the LRs, am I right? >> > > If you want to route *all* the interrupts, you can map GICC and not GICV > to your guest. So when the guest will read IAR, it will read the physical > interrupts. > > >> >> In case of GICv3, HCR_EL2.IMO will also control the access. So you >> should be fine here. >> >> However, in both case you will at least need to rework the way >> software generated interrupts are sent to the guest. At the moment, >> they are written in the LRs. >> >> Is it possible to not trap on the ICDSGIR (SGI register)? >> > > SGIs register are already trapped by Xen. They are emulated by writing the > corresponding interrupt to the LRs. > > How can make it available to the guest and not trap in Xen? Is it doable? > However, SGIs are not the only interrupt generated by the hypervisor > directly. There are also the event channel (a PPI) or any device emulated > by the hypervisor (e.g PL011). > > Trying to remove interrupts from the hypervisor is more a pain compare to > the benefits you will gain. You will be better at improving the latency > when receiving interrupt (AFAIK this is already be good). > > I changed the value of the HCR_EL2 register after doing a hypercall in "leave_hypervisor_tail" and now debugging. I realize that "guest_sync" in entry.S doesn't return back to the guest (I put a print after my hypercall in the guest and doesn't show up). I see that "return_from_trap" gets called. I suppose that eret should take me back to the hvc call I made in the guest. I checked the value of the LR register (link register that store the return address) in "return_from_trap" and there is no change. Do you know why changing the value of the HCR_EL2 register should affect returning back to the guest? Also, without changing the register value I get back to the guest from Xen normally. Cheers, > > -- > Julien Grall > Thanks a bunch! -- Saeed Mirzamohammadi PhD Student Department of Computer Science University of California, Irvine Irvine, CA 92617 sa...@uci.edu <smirz...@uci.edu> http://www.ics.uci.edu/~saeed/ <http://www.ics.uci.edu/~smirzamo/>
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