On Sun, 2011-03-06 at 14:05 +0800, arethe rtai wrote:
> As known, cache can accelerate the memory access, but
> unfortunately, it would decrease the predictability of real-time tasks'
> temporal behaviour. Many tasks of our application prefer
> predictability to the speed of execution. Intel's processors after P6
> include MTRR and PAT, both the two units can be used to bypass the
> I wonder whether Xenomai can bypass the cache, and whether Xenomai
> can manage the MTRR or PAT?
> If the answers are true, how to use the
> Xenomai-core mailing list
Xenomai-core mailing list